A reliability aware application mapping onto mesh based Network-on-Chip

Chatterjee, Navonil; Reddy, Sheshivardhan; Reddy, Shilpa; Chattopadhyay, Santanu

doi:10.1109/rait.2016.7507958

Cited by 7 publications

(12 citation statements)

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“…The deflection approach forced swarm particles to discover more solution space before converging to the global best result. A reliability aware model for mapping in NoC has been proposed in [79], where an amplified version of the standard PSO technique is used with a constructive heuristic to improve the reliability. The deterministic algorithms need significant computation time to explore the ideal mapping result.…”

Section: I) Transformative Heuristicsmentioning

confidence: 99%

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

et al. 2020

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Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the highperformance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip. I. INTRODUCTION System-on-Chip (SoC) is an archetype for the design and implementation of on-chip circuits that can support multiple systems on a single chip. The ever-rising number of processing cores on a single chip has made the efficiency of onchip designs as one of the major aspects in evaluating the average performance of embedded SoC. To fulfill the performance needs and to provide flexibility in the designs the field of Network on Chip (NoC) has emerged that separates the communication from the computation. Many surveys [1]-[7] are published in general and textbooks are also available on the topic [8]-[10]. There is still a need to solve more advanced research problems in NoC. Application mapping on NoC architecture has a prominent place among all the research problems which can be arbitrated from the published The associate editor coordinating the review of this manuscript and approving it for publication was Eyuphan Bulut. papers and current trends. This survey assumes a textbooklevel acquaintance of NoC terminology. The aim is to provide a comprehensive overview of all the aspects of application mapping (task graph generation, scheduling, optimization techniques, simulation setup, and performance evaluation metrics). The organization of this survey is as follows; first, we provide the reader the need and overview of application mapping in NoC presented in Section I. A detailed review and calcification of application mapping techniques in NoCs are discussed in Section II. The current and latest trends in application mapping are summarized in Section III. In Section IV performance comparison and the points that can create the difference between these techniques are highlighted. Finally, Section VI concludes this paper. A. MOTIVATION AND SCOPE Mostly synthetic traffic patterns are used to imitate the functionalities of rea...

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Section: I) Transformative Heuristicsmentioning

confidence: 99%

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

et al. 2020

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“…Several multi-objective approaches have been proposed to solve the NoC mapping problem (Ascia et al, 2005;Zhou et al, 2006;Jena & Sharma, 2007;Tornero et al, 2009;Nedjah et al, 2011;He & Guo, 2013;Zhu et al, 2015;Chatterjee et al, 2016;Bruch et al, 2017). Ascia et al (2005) present an approach for exploring the mapping design space while optimizing performance and power consumption by using SPEA2 (Ziztler et al, 2001) meta heuristic.…”

Section: Related Workmentioning

confidence: 99%

“…Another mapping approach is proposed by Zhu et al (2015) where a trade-off between temperature and latency is made. A constructive heuristic based method is proposed by Chatterjee et al (2016) to solve the mapping problem where both network communication cost and system reliability are optimized. Bruch et al, (2017) use NSGAII (Deb et al, 2002) meta-heuristic to find trade-off solutions that improve the deadline compliance, reduce both the number of virtual channels used in the routers and the static energy consumed by the network.…”

Section: Related Workmentioning

confidence: 99%

“…Bruch et al, (2017) use NSGAII (Deb et al, 2002) meta-heuristic to find trade-off solutions that improve the deadline compliance, reduce both the number of virtual channels used in the routers and the static energy consumed by the network. Some of the aforementioned works (He &Guo,2013;Zhu et al, 2015;Chatterjee et al, 2016) aggregate several objectives in a unified cost function. The drawback of these approaches comes from its difficulty to adjust the weights.…”

Section: Related Workmentioning

confidence: 99%

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Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid Algorithms

Belkacemi

Daoui

Bouzefrane

et al. 2019

International Journal of Distributed Systems and Technologies

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Mapping parallel applications onto a network on chip (NoC) that is based on heterogeneous MPSoCs is considered as an instance of an NP-hard and a multi-objective problem. Various multi-objective algorithms have been proposed in the literature to handle this issue. Metaheuristics stand out as highly appropriate approaches to deal with this kind of problem. These metaheuristics are classified into two sets: population-based metaheuristics and single solution-based ones. To take advantage of the both sets, the trend is to use hybrid solutions that have shown to give better results. In this article, the authors propose to hybridize these two metaheuristics sets to find good Pareto mapping solutions to optimize the execution time and the energy consumption simultaneously. The experimental results have shown that the proposed hybrid algorithms give high quality non-dominated mapping solutions in a reasonable runtime.

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“…To tolerate router faults the same research group in [9] has proposed a fault-tolerant NoC design in [10] using spare links and double network interface routers. The reliability aware application mapping method has been presented in [11] by proposing an integrated cost function to generate multiple solutions according to the requirements of the user. Although several studies have indicated that faults in cores, links and routers can be addressed using different techniques proposed in the literature, little attention has been paid to faults in cores of an application that has to be mapped onto NoC.…”

Section: Related Workmentioning

confidence: 99%

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

Bhanu

Kulkarni

Soumya

et al. 2018

2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-on-Chip (NoC) based communication architecture is introduced. In the nanoscale era NoCs are prone to faults which results in performance degradation and un-reliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. This paper presents a flexible spare core placement in torus topology based faulttolerant NoC design. The communications related to the failed core is taken care by selecting the best position for a spare core in the torus network. By considering this we propose a metaheuristic based Particle Swarm Optimization (PSO) technique to find suitable position for the spare core that minimizes the communication cost. We have experimented with several application benchmarks reported in the literature by varying the network size and by varying the fault-percentage in the network. The results show significant reduction in terms of communication cost compared to other approaches reported in literature.

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A reliability aware application mapping onto mesh based Network-on-Chip

Cited by 7 publications

References 12 publications

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid Algorithms

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

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