A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

Abstract

In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

“…Numerous methods for minimizing leakage power are reported in the literature [13][14][15][16][17][18][19][20] which are mostly based on modes of operation. They are classified into two categories: (1) Standby/Idle mode (2) Active mode…”