Abstract:Through silicon via (TSV) technology is widely used to achieve 3D integration of integrated circuits. Chemical mechanical planarization (CMP) is a mature technology to achieve both local and global planarization which can be applied in the traditional 1 st back side via reveal (BVR) process during the back side thinning and flattening of TSV wafers. In this paper, the surface and subsurface micro-damage of the TSV heterogeneous microstructure after back side CMP process was observed and characterized by cross-… Show more
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