A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference

Zhou, Zekun; Shi, Yue; Wang, Yao; Xiao, Zhuang; Wang, Yunkun; Liu, Xiaolin; Wang, Zhuo; Zhang, Bo

doi:10.1109/tcsi.2018.2857821

Cited by 40 publications

(27 citation statements)

References 37 publications

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“…When both of SBGRA and SBGRB are on, the variation range is 0.9 mV from -40~100 • C. Simply put, it is 2.6 ppm/ • C. The SBGRA and SBGRB output voltage cross at 30 • C. In -40 • C~30 • C temperature range, SBGRA output is higher than SBGRB's; in 30 • C~100 • C temperature range, the SBGRB output is higher than the SBGRA output. Table 2 reflects the comparison between this work with other previous work [3,5,6,[9][10][11]. Reference [9] presents superior TC, but requires three-point temperature trims which add a significant test cost.…”

Section: R5 R25mentioning

confidence: 99%

“…Table 2 reflects the comparison between this work with other previous work [3,5,6,[9][10][11]. Reference [9] presents superior TC, but requires three-point temperature trims which add a significant test cost. A ppm metric normalizes TC with respect to the VREF voltage.…”

Section: R5 R25mentioning

confidence: 99%

“…Another method utilizes two identical first-order bandgaps with different zero temperature points [7]. Other compensation methods, such as VBE linearization [8,9], temperature-dependent resistor ratio compensation [10], resistor-less, successive voltage step compensation [11], base current compensation [12], subthreshold compensation [13], and so on. However, some of these compensations rely upon the matching of transistor [3,14,15], resistor [3], the high beta bipolar [7], process stability or power supply voltage, etc.…”

Section: Introductionmentioning

confidence: 99%

“…Reference [7] requires high beta npn to obtain a high VREF voltage. For mass production, the multi-point temperature calibration must be implemented [6,8,9,11], therefore the test cost is significantly high.…”

Section: Introductionmentioning

confidence: 99%

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A 2.6 ppm/°C 2.5 V Piece-Wise Compensated Bandgap Reference with Low Beta Bipolar

et al. 2019

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Traditional bandgap reference (BGR) is sensitive to process variation and is not suitable for mass production. Consequently, a stacked piece-wise compensated bandgap reference (SPWBGR) with low beta bipolar is proposed, designed and fabricated in the 0.18 μm high-voltage (HV) BCD process. Two stacked BGR (SBGR) cores make up the proposed BGR circuit. Through setting the target reference voltage near the output voltage of SBGR cores, the feedback resistor ratio is reduced and the base current side-effect is significantly decreased. Notably, the SBGR core is implemented by the low beta npn bipolar and it relaxes the requirement for the high beta bipolar. The two SBGR cores are almost identical except for the temperature slope and feedback ratio. The two cores have different zero temperature coefficient (TC) points, one is set at −5 °C, and the other is set at 60 °C, named as SBGRA and SBGRB, respectively. The SBGRA and SBGRB output the same voltage at their zero TC point. The higher voltage of SBGRA and SBGRB is the output voltage. Through the process of tracking the maximum value of different SBGR cores, the proposed SPWBGR achieves 2.6 ppm/°C TC from −40 to 100 °C. As a result, the average TC for five random samples is 5.3 ppm/°C. The line regulation is 2 mV/V from 4.5 to 5.5 V power supply. The current consumption is 6.8 µA. The active area of the proposed BGR is 0.075 mm2.

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Section: R5 R25mentioning

confidence: 99%

Section: R5 R25mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 2.6 ppm/°C 2.5 V Piece-Wise Compensated Bandgap Reference with Low Beta Bipolar

et al. 2019

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“…Moreover, a survey of the literature reveals that resistor compensation schemes are typically utilized to realize low-temperature-coefficient (TC) voltage references (VRs) [6]- [11]. However, the usage of resistors can increase the chip area, cost, and noise coupled from the substrate [12]. From the research on the temperature characteristics of MOSFETs in [13], it was found that the gate-source voltage of a MOSFET with a fixed drain current bias can decrease with temperature.…”

Section: Introductionmentioning

confidence: 99%

A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS

2020

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This paper presents a low-power, low-voltage, and low-temperature-coefficient (TC) MOSFET-only subthreshold voltage reference circuit based on a standard 0.18-µm n-well CMOS process. The circuit consists of two novel current generators and an I/V conversion circuit with temperature compensation. Under the control of a proposed pMOS-bulk-driven (PBD) temperature compensation circuit, two pMOSFETs operating in a linear region act as resistors with different TCs and can be used for PTAT and CTAT current generation. Owing to the PBD technique and the subthreshold operating method, these two current generators and the I/V conversion circuit can operate at low voltage. The proposed reference circuit is realized with only standard V TH (SVT) MOS devices. The measurement results show that it can operate at a minimum supply voltage of 0.5 V. The line sensitivity is 0.09% for supply voltages between 0.5 and 1.8 V. The PSRR measured at 100 Hz is 51.8 dB. A measurement of 20 samples indicates that the average TC is 35.7 ppm/ • C across a temperature range of −40 to 85 • C. The proposed circuit consumes 17.6 nW from a 0.5-V power supply and occupies an active area of 0.0092 mm 2 .

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Subthreshold reference circuit with curvature compensation based on the channel length modulation of MOS devices

Aminzadeh

2021

Circuit Theory & Apps

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A subthreshold nano-power voltage and current reference with high-order temperature compensation is proposed by taking advantage of the channel length modulation of MOS devices. Curvature compensation is implemented by providing proper compensating drain-source voltages for the core devices of a first-order CMOS reference such that the output nonlinear temperature factors can be compensated over a wide temperature range. In-depth mathematical analysis is carried out to model the temperature dependency of the reference signals before and after compensation. As part of the analysis, Taylor expansion of the threshold voltage of MOS devices has been evaluated in a generalized fashion, enabling to clarify the complicated relationship between the high-order temperature-related terms of the output and design parameters. Simulated in a standard 0.18-μm CMOS process, the minimum supply voltage of a proof-of-concept design is 1.0 V, providing 345 mV voltage reference with minimum temperature coefficient (TC) of 2.0 ppm/ C across the range of -40-140 C. The active area is 0.45 mm 2 with around 200 nA current consumption. The DC line regulation is 0.23%/V, and the power supply rejection ratio (PSRR) is À63 dB at 10 Hz.

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A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference

Cited by 40 publications

References 37 publications

A 2.6 ppm/°C 2.5 V Piece-Wise Compensated Bandgap Reference with Low Beta Bipolar

A 2.6 ppm/°C 2.5 V Piece-Wise Compensated Bandgap Reference with Low Beta Bipolar

A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS

Subthreshold reference circuit with curvature compensation based on the channel length modulation of MOS devices

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