A retention-aware test power model for embedded SRAM

Abstract

This paper addresses the test power model problem for embeddedSRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of "zero" power consumption for the detection of Data Retention Faults. This paper takes advantage of this "zero" power period and proposes a "retention-aware" test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarios in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the "zero" power period is fully utilized in a SoC environment.

Retention-Aware Test Scheduling for BISTed Embedded SRAMs

“…This is due to the fact that test case 2 has only 15 large e-SRAMs, and when T pause ≥ 5M several e-SRAMs can be grouped into one scheduling unit 1 . As shown in Figure 3, the grouping happens in the horizonal direction and the testing time of the group becomes larger than the testing time of each individual e-SRAM.…”

“…Most prior work in test scheduling assumes a constant power consumption during the entire test process. Although simple and effective for logic testing, this model is overly pessimistic for e-SRAM testing when data retention faults (DRFs) are considered [1]. DRFs model the defects in SRAM bit cells that fails to retain a stored logic value.…”

“…During the two DRF pause time (for retention test of both logic '0' and logic '1'), no read/write operations are performed and hence it consumes nearzero test power. By taking this property into account, Wang et al [1] proposed a "retention-aware" test power model for testing built-in self-tested (BISTed) e-SRAMs, in which each e-SRAM test is represented by three rectangles A, B, and C with interval T AB and T BC , as shown in Figure 1. Empirical analysis is given in [1] that shows this model may significantly reduce the total e-SRAM testing time.…”

“…By taking this property into account, Wang et al [1] proposed a "retention-aware" test power model for testing built-in self-tested (BISTed) e-SRAMs, in which each e-SRAM test is represented by three rectangles A, B, and C with interval T AB and T BC , as shown in Figure 1. Empirical analysis is given in [1] that shows this model may significantly reduce the total e-SRAM testing time. However, automatic test scheduling algorithms are not provided in their work.…”

“…However, automatic test scheduling algorithms are not provided in their work. Therefore, in this paper, we propose "retention-aware" test scheduling techniques for e-SRAMs based on the test power model presented in [1]. Experimental results show that our approach significantly reduces the total testing time under given power constraints.…”