A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization

Yang, Fu-Ching; Chiang, Cheng-Lung; Huang, Ing-Jer

doi:10.1109/tvlsi.2009.2014872

Cited by 5 publications

(2 citation statements)

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“…In general this technology can be classified into trace-based and runstop-based approaches. The trace-based debug approach [3][4][5][6][7] records the information of the system during the normal system operation without stopping the system. Due to the limitations of the data transmission bandwidth and the memory space, the trace-based approach usually can only focus on a small part of a SoC and record the data in a short interval, and often requires some data compression schemes [3][4].…”

Section: Introductionmentioning

confidence: 99%

“…The trace-based debug approach [3][4][5][6][7] records the information of the system during the normal system operation without stopping the system. Due to the limitations of the data transmission bandwidth and the memory space, the trace-based approach usually can only focus on a small part of a SoC and record the data in a short interval, and often requires some data compression schemes [3][4]. The Run-stop debug approach [8][9][10][11][12] allows the user to set a breakpoint, run the system, and stop the system at the breakpoint.…”

Section: Introductionmentioning

confidence: 99%

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A High-Performance SoC Debug Platform

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Section: Introductionmentioning

confidence: 99%

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confidence: 99%

A High-Performance SoC Debug Platform

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A Versatile Data Cache for Trace Buffer Support

Lai

Yang

Huang

2014

IEEE Trans. Circuits Syst. I

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Architecture-Aware Real-Time Compression of Execution Traces

Mihajlović

Žilić

Gross

2015

ACM Trans. Embed. Comput. Syst.

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In recent years, on-chip trace generation has been recognized as a solution to the debugging of increasingly complex software. An execution trace can be seen as the most fundamentally useful type of trace, allowing the execution path of software to be determined post hoc. However, the bandwidth required to output such a trace can be excessive. Our architecture-aware trace compression (AATC) scheme adds an on-chip branch predictor and branch target buffer to reduce the volume of execution trace data in real time through on-chip compression. Novel redundancy reduction strategies are employed, most notably in exploiting the widespread use of linked branches and the compiler-driven movement of return addresses between link register, stack, and program counter. In doing so, the volume of branch target addresses is reduced by 52%, whereas other algorithmic improvements further decrease trace volume. An analysis of spatial and temporal redundancy in the trace stream allows a comparison of encoding strategies to be made for systematically increasing compression performance. A combination of differential, Fibonacci, VarLen, and Move-to-Front encodings are chosen to produce two compressor variants: a performance-focused xAATC that encodes 56.5 instructions/bit using 24,133 gates and an area-efficient fAATC that encodes 48.1 instructions/bit using only 9,854 gates.

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A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization

Cited by 5 publications

References 10 publications

A High-Performance SoC Debug Platform

A High-Performance SoC Debug Platform

A Versatile Data Cache for Trace Buffer Support

Architecture-Aware Real-Time Compression of Execution Traces

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