A reverse write assist circuit for SRAM dynamic write V&lt;inf&gt;MIN&lt;/inf&gt; tracking using canary SRAMs

Banerjee, Arijit; Sinangil, Mahmut E.; Poulton, John W.; Gray, C. Thomas; Calhoun, Benton H.

doi:10.1109/isqed.2014.6783299

Cited by 3 publications

(14 citation statements)

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“…In the year 2014, the authors in [23] demonstrated a theory for dynamic write V MIN tracking for the conventional 6T SRAM. This work introduces the term reverse assists (RA) as one of the canary design knobs.…”

Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

“…On the contrary, the RA Figure 7(a) degrades the writeability or readability of the canaries to fail earlier than the population of core SRAM, as shown in Figure 7(b). Thus, with the increase of the RA percentage, the canary distribution of write V MIN would shift to the right-hand side from distribution A to B to C. A user can tune the failure point of the canaries by selecting the proper reverse assist percentages or settings [23].…”

Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

“…The work also derives a mathematical formulation for dynamic write V MIN tracking as shown in Eqs. (1) and (2) [23]. Here the meanings of the variables of the equations are described in [23].…”

Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

“…(1) and (2) [23]. Here the meanings of the variables of the equations are described in [23]. Here, the two equations relate the input and output SRAM design knobs and metrics to the canary design knobs and metrics.…”

Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

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Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications

Banerjee¹

2018

Green Electronics

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Internet of Things (IoT) devices such as wearable health monitors, augmented reality goggles, home automation, smart appliances, etc. are a trending topic of research. Various IoT products are thriving in the current electronics market. The IoT application needs such as portability, form factor, weight, etc. dictate the features of such devices. Small, portable, and lightweight IoT devices limit the usage of the primary energy source to a smaller rechargeable or non-rechargeable battery. As battery life and replacement time are critical issues in battery-operated or partially energy-harvested IoT devices, ultralow-power (ULP) system on chips (SoC) are becoming a widespread solution of chip makers' choice. Such ULP SoC requires both logic and the embedded static random access memory (SRAM) in the processor to operate at very low supply voltages. With technology scaling for bulk and FinFET devices, logic has demonstrated to operate at low minimum operating voltages (V MIN). However, due to process and temperature variation, SRAMs have higher V MIN in scaled processes that become a huge problem in designing ULP SoC cores. This chapter discusses the latest published circuits and architecture techniques to minimize the SRAM V MIN for scaled bulk and FinFET technologies and improve battery life for ULP IoT applications.

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Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

Section: Canary Sensor Srams For V Min Tracking and Guardband Loweringmentioning

confidence: 99%

See 2 more Smart Citations

Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications

Banerjee¹

2018

Green Electronics

Self Cite

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“…In certain capacities, these latch arrays can be area-competitive with SRAMs as SRAMs typically require additional support circuitry [31]. Second, we are investigating read-assist and write-assist circuits that enable SRAMs to operate at voltages below their natural stability point [32], [33].…”

Section: Reduced-voltage Operationmentioning

confidence: 99%

Scaling the Power Wall: A Path to Exascale

Villa

Johnson

O'Connor³

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

100

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Abstract-Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.

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