A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

“…The process flow of Schottky S/D FinFETs is summarized in Figure 1 a. SOI wafers measuring 200 mm with top Si of 40 nm and BOX of 145 nm were used as the starting materials to mimic the bonded substrate of top-tier devices. The replacement metal gate (RMG) process was adopted, and all process steps were set below the typical thermal budget of 550 °C for compatibility with 3D sequential integration [ 3 , 4 , 5 ]. According to the principle of Schottky S/D MOSFETs [ 18 ], the electrical property is primarily determined by the Schottky junction barrier between S/D and channel.…”

“…This technology can enhance circuit density and functionality without the requirement of further reduction in device dimensions. To maintain the integrity of what is below, namely the bottom devices, interconnections and bonding interface, the thermal budget for top-tier fabrication is required to be no more than 550 °C [ 3 , 4 , 5 ].…”

Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2

“…This limitation is imposed by gate work function instability and silicide contact degradation . Certain interlayer low-κ dielectrics (e.g., SiCOH) could require even lower thermal budgets, below 450 °C for 2 h, although SiCOH integrity could be maintained up to 525 °C for 2 h using some BEOL processes . Thus, in order to incorporate new materials such as MoS 2 into stacked, heterogeneous integrated circuits that increase the transistor density in the third dimension, their BEOL thermal budget becomes crucial.…”

“…27 Certain interlayer low-κ dielectrics (e.g., SiCOH) could require even lower thermal budgets, below 450 °C for 2 h, 21 although SiCOH integrity could be maintained up to 525 °C for 2 h using some BEOL processes. 24 Thus, in order to incorporate new materials such as MoS 2 into stacked, heterogeneous integrated circuits that increase the transistor density in the third dimension, 35 their BEOL thermal budget becomes crucial. However, direct monolayer (1L) MoS 2 growths with good electrical properties have typically been obtained using solid-source precursor CVD above 650 °C.…”

“…Specifically, MoS 2 has become one of the most promising TMDs due to its band gap (∼2.2 eV for monolayer MoS 2 , ) and controllable growth of consistent large-area MoS 2 films down to monolayer (1L) thicknesses, making MoS 2 a viable candidate for large-scale semiconductor applications. − Although moving MoS 2 away from tedious and inconsistent mechanical exfoliation techniques has enabled systematic studies for electronics applications, ,, the quality of synthesized MoS 2 has not always been ideal, especially from the standpoint of the device fabrication thermal budget. If MoS 2 is to be integrated in the back end (i.e., after silicon) of modern integrated circuits, the fabrication process of as-grown MoS 2 transistors cannot exceed the range of 450–600 °C (depending on the process time) for integration with logic applications, − although some three-dimensional (3D) vertical memory applications can withstand >700 °C . For example, irreversible degradation of certain silicide contacts, interlayer dielectrics, and diffusion barrier layers have been observed with thermal budgets over 600 °C for 2 h. ,, …”