No abstract

3-D sequential integration stands out from other 3-D schemes as it enables the full use of the third dimension. Indeed, in this approach, 3-D contact density matches with the transistor scale. In this paper, we report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes ( C) and salicide stabilization achievements. This integration scheme enables fine grain partitioning and thus a gain in performance versus cost ratio linked to separation of heterogeneous technologies on distinct levels. In this work, we will detail examples taking advantage of the unique 3-D contact pitch achieved with sequential 3-D.Index Terms-Low temperature process, molecular bonding, solid phase epitaxy, three-dimensional (3-D) integration, 3-D monolithic integration, 3-D sequential integration.