A Review of Near-Memory Computing Architectures: Opportunities and Challenges

Singh, Gagandeep; Chelini, Lorenzo; Corda, Stefano; Awan, Ahsan Javed; Stuijk, Sander; Jordans, Roel; Corporaal, Henk; Boonstra, Albert‐Jan

doi:10.1109/dsd.2018.00106

Cited by 83 publications

(50 citation statements)

References 59 publications

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“…Near Memory Processing (NMP) is the practice of placing compute logic near memory, generally DRAM, in an effort to decrease access time [4]. Many architectures allocate compute blocks on the logic layer of HMC DRAM [12], [13], [14], [15].…”

Section: Near Memory Processing (Nmp)mentioning

confidence: 99%

“…While NMP computing shows promise, there is still much research to be done to validate its feasibility. First, from an integration standpoint, NMP poses a challenge in regards to virtual-physical memory translation and managing cache coherency [4]. Second, from an application viewpoint, few works provide potential solutions for optimizing algorithms to utilize NMP units while accounting for data locality [17], [21].…”

Section: Near Memory Processing (Nmp)mentioning

confidence: 99%

“…A S edge devices are being increasingly utilized to perform compute intensive tasks traditionally reserved for servers with access to standard accelerators such as GPUs [1], [2], a wide range of compute architectures that are specially suited for edge devices' area and power constraints have been proposed. One such innovation is the concept of near or in-memory computing [3], [4], which improves performance by computing at the point of data storage. Such architectures are placed near DRAM, within the cache hierarchy, or as separate accelerator units with dedicated memory arrays.…”

Section: Introductionmentioning

confidence: 99%

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BLADE: An in-Cache Computing Architecture for Edge Devices

Simon

Qureshi

Rios

et al. 2020

IEEE Trans. Comput.

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Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spatially local data common in many emerging workloads, while reducing power consumption due to data movement. However, in-SRAM computing faces many challenges, including integration into the existing architecture, arithmetic operation support, data corruption at high operating frequencies, inability to run at low voltages, and low area density. To meet these challenges, this work introduces BLADE, a BitLine Accelerator for Devices on the Edge. BLADE is an in-SRAM computing architecture that utilizes local wordline groups to perform computations at a frequency 2.8x higher than state-of-the-art in-SRAM computing architectures. BLADE is integrated into the cache hierarchy of low-voltage edge devices, and simulated and benchmarked at the transistor, architecture, and software abstraction levels. Experimental results demonstrate performance/energy gains over an equivalent NEON accelerated processor for a variety of edge device workloads, namely, cryptography (4x performance gain/6x energy reduction), video encoding (6x/2x), and convolutional neural networks (3x/1.5x), while maintaining the highest frequency/energy ratio (up to 2.2Ghz@1V) of any conventional in-SRAM computing architecture, and a low area overhead of less than 8%.

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Section: Near Memory Processing (Nmp)mentioning

confidence: 99%

Section: Near Memory Processing (Nmp)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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BLADE: An in-Cache Computing Architecture for Edge Devices

Simon

Qureshi

Rios

et al. 2020

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…Earlier works, e.g., [10,11,12], focused on devising architectures that placing processing cores with dynamic random-access memory (DRAM) modules. These architectures generally belong to the category of near-memory computing (NMC) [29]. However, practical concerns regarding the successful integration of DRAM and processing units into the same chip have hindered the advancement of such NMC systems for many years.…”

Section: Computing In Memorymentioning

confidence: 99%

Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures

Gao

Reis

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Computing-in-Memory (CiM) architectures aim to reduce costly data transfers by performing arithmetic and logic operations in memory and hence relieve the pressure due to the memory wall. However, determining whether a given workload can really benefit from CiM, which memory hierarchy and what device technology should be adopted by a CiM architecture requires in-depth study that is not only time consuming but also demands significant expertise in architectures and compilers. This paper presents an energy evaluation framework, Eva-CiM, for systems based on CiM architectures. Eva-CiM encompasses a multi-level (from device to architecture) comprehensive tool chain by leveraging existing modeling and simulation tools such as GEM5 [1], McPAT [2] and DESTINY [3]. To support high-confidence prediction, rapid design space exploration and ease of use, Eva-CiM introduces several novel modeling/analysis approaches including models for capturing memory access and dependencyaware ISA traces, and for quantifying interactions between the host CPU and CiM modules. Eva-CiM can readily produce energy estimates of the entire system for a given program, a processor architecture, and the CiM array and technology specifications. Eva-CiM is validated by comparing with DESTINY [3] and [4], and enables findings including practical contributions from CiM-supported accesses, CiM-sensitive benchmarking as well as the pros and cons of increased memory size for CiM. Eva-CiM also enables exploration over different configurations and device technologies, showing 1.3-6.0× energy improvement for SRAM and 2.0-7.9× for FeFET-RAM, respectively.

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“…Furthermore, the improvements in memory and processor technology have grown at different speeds, which is infamously termed as the memory wall [11]. Additionally, the current big-data era, where data is being generated in a massive amount and across multiple domains, has created a demand for novel memory-centric designs rather than conventional compute-centric designs [9].…”

Section: Introductionmentioning

confidence: 99%

Memory and Parallelism Analysis Using a Platform-Independent Approach

Corda

Singh

Awan

et al. 2019

Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems

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Emerging computing architectures such as near-memory computing (NMC) promise improved performance for applications by reducing the data movement between CPU and memory. However, detecting such applications is not a trivial task. In this ongoing work, we extend the state-of-the-art platform-independent software analysis tool with NMC related metrics such as memory entropy, spatial locality, data-level, and basic-block-level parallelism. These metrics help to identify the applications more suitable for NMC architectures. CCS CONCEPTS• Software and its engineering → Dynamic analysis.

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A Review of Near-Memory Computing Architectures: Opportunities and Challenges

Cited by 83 publications

References 59 publications

BLADE: An in-Cache Computing Architecture for Edge Devices

BLADE: An in-Cache Computing Architecture for Edge Devices

Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures

Memory and Parallelism Analysis Using a Platform-Independent Approach

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