XI Brazilian Power Electronics Conference 2011
DOI: 10.1109/cobep.2011.6085334
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A review of the main inverter topologies applied on the integration of renewable energy resources to the grid

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Cited by 12 publications
(9 citation statements)
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“…Many new topologies of inverter had been developed (Paulino et al 2011;Arif, Bin, and Md Ayob 2014). For the case study purpose, a 15 kW capacity inverter is used which can operate simultaneously with a generator.…”
Section: Dc/ac Converter or Invertermentioning
confidence: 99%
“…Many new topologies of inverter had been developed (Paulino et al 2011;Arif, Bin, and Md Ayob 2014). For the case study purpose, a 15 kW capacity inverter is used which can operate simultaneously with a generator.…”
Section: Dc/ac Converter or Invertermentioning
confidence: 99%
“…The operational principle of HB-ZVR topology is very similar to the HERIC topology [72]. The gate pulse of S5 in the positive half-wave is the contrary gate pulse of S1 and S4, with a small dead time to neglect grid short circuit [25,76]. During the negative half wave, S5 is controlled using the contrary gate pulse of S2 and S3 and creates zero-voltage state by short-circuiting the output of the inverter and clamping them to the mid-point of the DC bus.…”
Section: Hb-zvr Topologymentioning
confidence: 99%
“…However, a current sensor is not required in the presented experimental [2,4] voltage (1 V/div), time (4 ms/div) b Reference voltage for leg A, output of the real-time integrator, reset signal and PWM signal for MOSFET S1, v RefA (t) and v RefB (t), scale: [2] voltage (2 V/div), [1,3] voltage (5 V/div), time (10 μs/div) c Output voltage of each leg of the inverter, v A (t) and v B (t), scale: [1] voltage (50 V/div), time (4 ms/div) d Inverter output voltage, inverter output current, and grid voltage; v o (t), i o (t) and v Grid (t), scale: [3] voltage (100 V/div), [3] current (5 A/div), time (4 ms/div) Fig. 8 Dynamic response at transient time from without-load to with-load condition, scale: [1,3] voltage (100 V/div), [4] current (5 A/div), time (10 ms/div) Furthermore, compared with current mode, it can result lower switching current noise and will lead to lower EMI. As for the efficiency system, the presented DBI prototype cannot achieve CEC efficiency more than 83%, since the hard switching technique is used in this experiment.…”
Section: Experimental Verificationmentioning
confidence: 99%
“…OCC reference signal and output voltage of the inverter a Sinusoidal reference, scaled grid voltage and its differentiation; v Ref ( t ), av Grid ( t ) and v Diff ( t ), scale: [2, 4] voltage (1 V/div), time (4 ms/div) b Reference voltage for leg A, output of the real‐time integrator, reset signal and PWM signal for MOSFET S1, v Ref A ( t ) and v Ref B ( t ), scale: [2] voltage (2 V/div), [1, 3] voltage (5 V/div), time (10 μs/div) c Output voltage of each leg of the inverter, v A ( t ) and v B ( t ), scale: [1] voltage (50 V/div), time (4 ms/div) d Inverter output voltage, inverter output current, and grid voltage; v o ( t ), i o ( t ) and v Grid ( t ), scale: [3] voltage (100 V/div), [3] current (5 A/div), time (4 ms/div)…”
Section: Experimental Verificationmentioning
confidence: 99%
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