A Review of Three‐Dimensional Resistive Switching Cross‐Bar Array Memories from the Integration and Materials Property Points of View

Abstract

Issues in the circuitry, integration, and material properties of the two-dimensional (2D) and three-dimensional (3D) crossbar array (CBA)-type resistance switching memories are described. Two important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the increased area and layout complexity of the periphery circuits. The sneak current problem can be mitigated by the adoption of different voltage application schemes and various selection devices. These have critical correlations, however, and depend on the involved types of resistance switching memory. The problem is quantitatively dealt with using the generalized equation for the overall resistance of the parasitic current paths. Atomic layer deposition is discussed in detail as the most feasible fabrication process of 3D CBAs because it can provide the device with the necessary conformality and atomic-level accuracy in thickness control. Other subsidiary issues related to the line resistance, maximum available current, and fabrication technologies are also reviewed. Finally, a summary and outlook on various other applications of 3D CBAs are provided.

Reliable current changes with selectivity ratio above 109 observed in lightly doped zinc oxide films

“…In addition to planar cross-point arrays, three-dimensional stackable cross-point arrays have been recently considered to maximize ReRAM density. 8,9 However, the ReRAM cross-point array has critical problems with sneak current and unnecessary power consumption from neighboring memory cells. In general, ReRAMs are operated by measuring the current difference between a metallic low-resistance state (LRS) and an insulating high-resistance state (HRS).…”

“…Thus, the leakage current from the LRS cells of an ReRAM leads to current sensing failure during the reading of HRS cells. 8 To overcome the leakage current issue, the mixed-ionicelectronic conduction (MIEC) selector was developed by IBM. 10,11 The MIEC is widely accepted as a nearly ideal selector because it shows low off-current (100 pA), high on-current (10 μA) and steep subthreshold swing characteristics (o60 mV per decade).…”

Practical Determination of Individual Element Resistive States in Selectorless RRAM Arrays

“…Sneak currents can be mitigated in selectorless arrays too by e.g. employing suitable biasing regimes (for overview of such biasing regimes see section 2.6 in [13]) or attempting to calculate cross-point resistance via multiple, multi-port measurements [14]. Each mitigation/readout strategy has merits and drawbacks.…”

An FPGA-Based Instrument for En-Masse RRAM Characterization With ns Pulsing Resolution

“…1(b). This simplifies analysis [9] and is based on a connectivity feature employed by most, common crossbar biasing schemes [10]. However, even an ideal crossbar configuration suffers from the issue of sneak paths [11], where a voltage applied to a target device causes current to flow through unselected devices within the crossbar.…”

“…As a result, cell read-out accuracy is reduced and write operations may disturb the memory state of adjacent devices, which is why strategies to mitigate sneak path effects are an area of active research. These include introducing CMOS [12], or emerging devices [13] as 'selector' elements to isolate the target device from the rest of the array, and the employment of active biasing of inactive WLs and BLs in order to divert sneak currents [10] amongst other techniques [14]. The second key advantage of RRAM concerns the potential for single-device, multi-level memory cells [2].…”