Issues in the circuitry, integration, and material properties of the two-dimensional (2D) and three-dimensional (3D) crossbar array (CBA)-type resistance switching memories are described. Two important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the increased area and layout complexity of the periphery circuits. The sneak current problem can be mitigated by the adoption of different voltage application schemes and various selection devices. These have critical correlations, however, and depend on the involved types of resistance switching memory. The problem is quantitatively dealt with using the generalized equation for the overall resistance of the parasitic current paths. Atomic layer deposition is discussed in detail as the most feasible fabrication process of 3D CBAs because it can provide the device with the necessary conformality and atomic-level accuracy in thickness control. Other subsidiary issues related to the line resistance, maximum available current, and fabrication technologies are also reviewed. Finally, a summary and outlook on various other applications of 3D CBAs are provided.

The development of a resistance switching (RS) memory cell that contains rectifi cation functionality in itself, highly reproducible RS performance, and electroforming-free characteristics is an impending task for the development of resistance switching random access memory. In this work, a two-layered dielectric structure consisting of HfO 2 and Ta 2 O 5 layers, which are in contact with the TiN and Pt electrode, is presented for achieving these tasks simultaneously in one sample confi guration. The HfO 2 layer works as the resistance switching layer by trapping or detrapping of electronic carriers, whereas the Ta 2 O 5 layer remains intact during the whole switching cycle, which provides the rectifi cation. With the optimized structure and operation conditions for the given materials, excellent RS uniformity, electroforming-free, and selfrectifying functionality could be simultaneously achieved from the Pt/Ta 2 O 5 / HfO 2 /TiN structure.

The detailed mechanism of electronic bipolar resistance switching (BRS) in the Pt/TiO(2)/Pt structure was examined. The conduction mechanism analysis showed that the trap-free and trap-mediated space-charge-limited conduction (SCLC) governs the low and high resistance state of BRS, respectively. The SCLC was confirmed by fitting the current-voltage characteristics of low and high resistance states at various temperatures. The BRS behavior originated from the asymmetric potential barrier for electrons escaping from, and trapping into, the trap sites with respect to the bias polarity. This asymmetric potential barrier was formed at the interface between the trap layer and trap-free layer. The detailed parameters such as trap density, and trap layer and trap-free layer thicknesses in the electronic BRS were evaluated. This showed that the degradation in the switching performance could be understood from the decrease and modified distribution of the trap densities in the trap layer.

Limiting the location where electron injection occurs at the cathode interface to a narrower region is the key factor for achieving a highly improved RS performance, which can be achieved by including Ru Nanodots. The development of a memory cell structure truly at the nanoscale with such a limiting factor for the electric-field distribution can solve the non-uniformity issue of future ReRAM.