A Review on RF ESD Protection Design

A Dual-Polarity Graphene NEMS Switch ESD Protection Structure

“…The accurate relationship between V t1 and gNEMS switch dimensions requires more research to improve the fabrication processes and device quality. Figure 5 depicts a near symmetric switching I-V behavior, which is highly desirable for full-chip ESD protection to reduce ESD device head counts [1], hence ESD area size and parasitic effects. Measurement shows ultra-low leakage of I leak ∼3-13pA at DC bias of 0.5-3V expected for normal IC operations.…”

“…The super mechanical strength of graphene also ensure high ESD robustness. Ideally, a gNEMS switch is a dual-polarity device that can significantly reduce the total ESD device head counts in ICs [1]. A big advantage of gNEMS ESD switch is that, because it is an above-IC device, the new gNEMS ESD structures can be placed above Si ICs through 3D heterogeneous integration.…”

“…For decades, conventional ESD protection structures relied on PN-junction-based device structures inside silicon to provide active paths to discharge fast ESD transients safely. In principle, an ESD protection structure is a switch that may be turned on by an ESD transient to shunt ESD surges [1]. ESD protection structures are characterized by ESD-critical parameters including triggering voltage, current and time (V t1 , I t1 , t 1 ), holding voltage and current (V h , I h ), discharging resistance (R ON ), and failure voltage and current (V t2 , I t2 ) [1]- [3].…”

“…In principle, an ESD protection structure is a switch that may be turned on by an ESD transient to shunt ESD surges [1]. ESD protection structures are characterized by ESD-critical parameters including triggering voltage, current and time (V t1 , I t1 , t 1 ), holding voltage and current (V h , I h ), discharging resistance (R ON ), and failure voltage and current (V t2 , I t2 ) [1]- [3]. However, in-Si PN-type ESD protection structures have inherent disadvantages such as parasitic junction leakage (I leak ), easily being a few tens of nA for typical ESD structures and becoming intolerable to ICs at nano nodes [3]- [5].…”

High Performance ESD/Surge Protection Capability of Bidirectional Flip Chip Transient Voltage Suppression Diodes

“…[1][2][3] The phenomenon of ESD leads to permanent device damage associated with the breakdowns of junctions, metal interconnects and dielectrics, caused by high current transients and high voltage overstress. Nowadays, IC dimensions have been continuously scaled down to realize higher packing density, faster operation speed and lower power dissipation.…”