A RISC-V instruction set processor-micro-architecture design and analysis

Raveendran, Aneesh; Patil, Vinayak; Selvakumar, David; Desalphine, Vivian

doi:10.1109/vlsi-sata.2016.7593047

Cited by 23 publications

(6 citation statements)

References 4 publications

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“…RISC-V processors [1]- [11] are distinguished by the concise open-source RISC-V instruction set architecture (ISA) [12], which defines a fundamental set of instructions while offering opportunities to incorporate application-specific custom instructions. This unique feature enables RISC-V processors as a promising solution ranging from energy-efficient embedded systems [10] to high-throughput servers [1].…”

Section: Introductionmentioning

confidence: 99%

School of Teacher, Nanjing Xiao Zhuang University, Nanjing, 210000, China

Wang¹

2017

Advances in Psychological Science

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The nuclide 14 C can be produced in the atmosphere by high energy particles and γ-rays from high-energy phenomena. Through the carbon cycle, some of 14 CO 2 produced in the atmosphere can be retained in annual tree rings 1, 2 . Four events of rapid increase of the 14 C content occurred in AD 775, AD 994, BC 660 and BC 3371 were found 3-6 . Recently, the data of Jull et al. (2020) was inconsistent with our records around BC 3371. We measured our sample again and found the 14 C records are consistent with the value in Wang et al. (2017). Therefore, our 14 C records are robust. The inconsistency may be caused by the difference of calendar ages for the wood samples, or the physical origin of the event. First, crossdating on ring width can be performed only between trees whose growth has the same environmental conditions. Because the master tree-ring for dendrochronology is lack for Chinese trees. The master tree-ring from California has to be used. Therefore, the calendar ages derived from dendrochronology may be not precise. Second, the 14 C even may be not global. One evidence

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Section: Introductionmentioning

confidence: 99%

School of Teacher, Nanjing Xiao Zhuang University, Nanjing, 210000, China

Wang¹

2017

Advances in Psychological Science

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“…The format of the mpl register is defined as shown in Figure 3. To reduce the time consumption of finding the entry address of interrupt service program, the design uses the vector table approach for jumping [10] , and the interrupt service program and the exception service program share one entry address [11,12] , which is stored in the mtvec register. To further reduce the time consumption caused by finding the interrupt vector table when finding the exception service program, a special CSR register misr is defined for interrupts to save the entry addresses of all interrupts, and the format of the relevant misr register is defined as shown in Figure 4.…”

Section: Preemption Level Register Mpl and Interrupt Service Program ...mentioning

confidence: 99%

Design and implementation of a fast interrupt system based on RISC-V

Zhang,

Shang

et al. 2023

Second International Conference on Electronic Information Technology (EIT 2023)

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Interrupt technology is a key technology for processors to respond to external events and plays an important role in the embedded field.The open source RISC-V architecture defines a complete set of interrupt mechanisms with hardware definitions that do not support interrupt nesting in embedded systems that only support machine mode, and software support for interrupt nesting adds additional time overhead.This paper is based on the interrupt mechanism defined by RISC-V, using a state machine to control the global interrupt enablement of the processor to support interrupt nesting, and to save the site and restore the site through hardware stacking and out-stacking to avoid the time consumption caused by the software level;A dedicated entry point for interrupt service program jumps further speeds up the response. In this paper, we design and implement a fast interrupt system using Hummingbird E203, an open source kernel defined by standard RISC-V, as an experimental platform.Simulation verification and comprehensive implementation on FPGA platform show that compared to the interrupt handling process of Hummingbird E203, using a small amount of hardware resource consumption, the response speed is improved by 1/4, providing better real-time performance and flexibility in embedded applications.

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“…Xuantie-910 [17] RISC-V processor is a 64-bit out of order execution 12-stage pipeline releases high efficient vector processing, supports multi core processor, delivers high performance compared to its predecessor belonging to RISC-V family. The design [18] has been emphasized on instructions encoding, instruction functionalities, instruction types, decoder logic complexity, data hazard detection, register file organization and access, pipeline operation, impact of branch instructions, control flow, data memory access, operating modes, and hardware resources for the execution unit. Bit flips in digital systems causes threats, well known as soft errors.…”

Section: Related Workmentioning

confidence: 99%

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

Preethi¹,

G²,

Augustine³

et al. 2022

INDJCSE

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In microprocessor architecture, amid a few blocks outcome of the optimized sorting algorithm has proved its impact on the results. Sorters can be implemented in domains that includes data centers, cloud computing servers for IoT applications. Sorters can be implemented on hardware, by deploying the developed sorter on Field Programmable Gate Array (FPGA). By contrasting factors like power consumption, implementation time, and implementation space with those of the proposed algorithm, it is possible to show the shortcomings of existing sorters like Bubble sort, Bitonic sort, and Odd-Even sort. This approves that the sorter with higher capability will perform better for sorting involving large numbers, this helps in designing of large-scale sorting for aforementioned applications. Few sorters were compared based on the parameters and it was concluded that comparison-free odd-even was having upper hand. Hence, the optimized sorter was implemented on the MicroBlaze, which is based on RISC-V architecture.

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A RISC-V instruction set processor-micro-architecture design and analysis

Cited by 23 publications

References 4 publications

School of Teacher, Nanjing Xiao Zhuang University, Nanjing, 210000, China

School of Teacher, Nanjing Xiao Zhuang University, Nanjing, 210000, China

Design and implementation of a fast interrupt system based on RISC-V

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

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