Floating point operations are important and essential part of many scientific and engineering applications. Floating point coprocessor (FPU) performs operations like addition, subtraction, division, square root, multiplication, fused multiply and accumulate and compare. Floating point operations are part of ARM, MIPS, and RISC-V etc. instruction sets. The FPU can be a part of hardware or be implemented in software. This paper details an architectural exploration for floating point coprocessor enabled with RISC-V [1] floating point instructions. The Floating unit that has been designed with RISC-V floating point instructions is fully compatible with IEEE 754-2008 standard as well. The floating point coprocessor is capable of handling both single and double precision floating point data operands in out-of-order for execution and in-order commit. The front end of the floating point processor accepts three data operands, rounding mode and associated Opcode fields for decoding. Each floating point operation is tagged with an instruction token for in-order completion and commit. The output of the floating point unit is tagged with either single or double precision results along with floating point exceptions, if any, based on the RISC-V instruction set. The coprocessor for floating point integrates with integer pipeline. The proposed architecture for floating point coprocessor with out-of-order execution, in-order commit and completion/retire has been synthesized, tested and verified on Xilinx Virtex 6 xc6vlx550t-2ff1759 FPGA. A system frequency of 240MHz for single precision floating point and 180 MHz double precision floating point operations has been observed on FPGA. Index Terms-IEEE 754 floating point standard, floating point co-processor, RISC processor, RISC-V instruction set, Microprocessor.

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Data conversion operations are important and essential part of floating point units in a processor and typical instructions include conversion between various precisions, integer to floating point and vice versa, floating point to fixed point and vice versa etc. Besides few processors have instructions to round and truncate data, sign injections, move data between co-processors registers and general purpose registers and vice versa etc. Conversion operations are part of ARM, MIPS, and RISC-V etc. instruction sets. The conversion functionalities can be part of hardware or may be implemented in software. This paper details an architectural exploration for data conversion coprocessor for RISC-V [1] data conversion instructions. The Floating point conversion unit that has been designed with RISC-V data conversion instructions is fully compatible with IEEE 754-2008 standard as well. The floating point conversion co-processor is capable of handling both single and double precision floating point data operands in out-of-order for execution and in-order commit. The front end of the data conversion processor accepts three data operands, rounding mode and associated Op-code fields for decoding. Each conversion operation is tagged with an instruction token for in-order completion and commit. The output of the floating point unit is tagged with either single or double precision results along with floating point exceptions if any, based on the RISC-V instruction set. The co-processor for data conversion integrates with integer pipeline. The proposed architecture for data conversion co-processor with out-of-order execution, in-order commit and completion / retire has been synthesized, tested and verified on Xilinx Virtex 6 xc6vlx550t-2ff1759 FPGA. A performance throughput of 350MFLOPs (data conversion operations) per second have been observed. Index Terms-IEEE 754-2008 floating point standard, floating point co-processor, RISC processor, RISC-V instruction set, Outof-order and Microprocessor.