HMFPCC: - Hybrid-mode floating point conversion co-processor

Aneesh, R; Patil, Vinayak; Pm, Sobha; Selvakumar, Anith

doi:10.1109/vlsi-sata.2015.7050482

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2023

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“…FFICIENT hardware implementations of leading zero counters (LZCs) are required in several applications, like the floating-point arithmetic computations [1], [2], the conversion of floating-point data to other formats [3], the design of mixed-precision computational units [4], the quantization of Deep Neural Networks (DNNs) [5] and the probabilistic approximate computing [6], just to cite some representative examples.…”

Section: Introductionmentioning

confidence: 99%

Design of Leading Zero Counters on FPGAs

Perri

Spagnolo

Frustaci

et al. 2023

IEEE Embedded Syst. Lett.

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This letter presents a novel leading zero counter (LZC) able to efficiently exploits the hardware resources available within state-of-the-art FPGA devices to achieve high speed performances with limited energy consumption. Postimplementation results, obtained for operands bit-widths varying between 4-and 64-bit, demonstrate that the new design improves its direct competitors in terms of occupied lookup tables (LUTs), power consumption and computational speed. As an example, when implemented using the Xilinx Artix-7 xc7a100tcsg324 device, the new 64-bit LZC utilizes up to 36% less LUTs, dissipates up to 2.8 times lower power and is up to 20% faster than state-ofthe-art counterparts.

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