A Robust 10 kV SiC MOSFET Gate Driver with Fast Overcurrent Protection Demonstrated in a MMC Submodule

Huang, Xingxuan; Ji, Shiqi; Palmer, James; Zhang, Li; Li, Dingrui; Wang, Fred; Tolbert, Leon M.; Giewont, William

doi:10.1109/apec39645.2020.9124533

Cited by 11 publications

(10 citation statements)

References 15 publications

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“…With a voltage divider and a discrete comparator, the desat protection based on discrete components in Fig. 1(a) has more flexibility to achieve a desired response time and threshold current for various high voltage SiC MOSFETs [13], [21]. Vcc in Fig.…”

Section: Noise Immunity Analysismentioning

confidence: 99%

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Comprehensive Analysis and Improvement Methods of Noise Immunity of Desat Protection for High Voltage SiC MOSFETs With High DV/DT

Huang

Nie

et al. 2022

IEEE Open J. Power Electron.

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This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high dv/dt. This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive dv/dt and negative dv/dt are investigated. Analysis results show that the high dv/dt with long duration caused by high voltage SiC MOSFETs' switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive dv/dt, extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive dv/dt is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.

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Section: Noise Immunity Analysismentioning

confidence: 99%

“…1(a), since Vcomp is not clamped by a diode. In this paper, the desat protection circuitry designed for the 10 kV/20 A SiC MOSFET from Wolfspeed is studied as an example [21]. Parameters of the desat protection circuitry are shown in Fig.…”

Section: Noise Immunity Analysismentioning

confidence: 99%

Comprehensive Analysis and Improvement Methods of Noise Immunity of Desat Protection for High Voltage SiC MOSFETs With High DV/DT

Huang

Nie

et al. 2022

IEEE Open J. Power Electron.

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“…The paper [26] proposed a desaturation detection circuit with adjustable DESAT reference voltage by adding the extra DESAT diode. The paper [27] utilized digital ICs to generate the easily configurable blanking time for SiC MOSFET gate driver circuit. In [28], a resistor connecting the blanking capacitor and the gate of SiC MOSFET is added to accelerate the charging of the blanking capacitor to reduce the blanking time.…”

Section: Introductionmentioning

confidence: 99%

A short circuit protection circuit for SiC MOSFET with self-adjustive blanking time

Liu

Quan

Zhou

et al. 2021

IEICE Electron. Express

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This paper proposed a desaturation (DESAT) short circuit (SC) protection circuit for SiC MOSFET, where a blanking time setting module and an SC detection module are designed. The fall time of the drain-source voltage (VDS) for each switching period of SiC MOSFET is recorded and set as the blanking time for the hard switching fault (HSF) detection in the next switching period. Consequently, the detection delay for HSF is self-adjustive and can respond quickly to the operating state of SiC MOSFET. FPGA and discrete components are used to implement the proposed circuit. The function of the proposed circuit is verified using the double pulse test. The experiment results show that the blanking time automatically increases with the increase of load current. The default detection delay of the proposed protection circuit is set 240ns for HSF and can be adjusted during the subsequent switching period. So in the test under a 400V bus voltage, the detection delay is 240ns for HSF at the first switching period. And for HSF occurs at the second switching period, the detection delay is 200ns adjusted according to the operating state of the first switching period. Meanwhile, the detection delay for fault under load (FUL) is 72 ns.

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“…1(b). The signal isolation of GDs can be implemented by the GD integrated circuit (GDIC) [7], digital isolator [8], transformer [9], and fiber-optic (FO) [10]- [15]. For MV SiC MOSFETs, FOs are usually adopted to transmit the signal with a sufficient galvanic isolation and little coupling capacitance C cp on the signal path but with a size and cost penalty [10]- [15].…”

mentioning

confidence: 99%

“…The signal isolation of GDs can be implemented by the GD integrated circuit (GDIC) [7], digital isolator [8], transformer [9], and fiber-optic (FO) [10]- [15]. For MV SiC MOSFETs, FOs are usually adopted to transmit the signal with a sufficient galvanic isolation and little coupling capacitance C cp on the signal path but with a size and cost penalty [10]- [15]. Like the other signal-isolation method based GDs, secondary circuits of the FO-based GD are tied to the source terminal of SiC MOSFET, the signal-processing circuit is therefore susceptible to the common-mode (CM) current noise induced by the high dv/dt and may be malfunctioning [10].…”

mentioning

confidence: 99%

A MHz-Pulse-Transformer Isolated Gate Driver With Signal-Power Integrated Transmission for Medium-Voltage SiC MOSFETs

Guo

2022

IEEE Trans. Power Electron.

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The conventional isolated gate driver (GD) solution for the medium-voltage (MV) SiC MOSFET separates the signal and power transmissions and requires a bulky GD power supply (GDPS). This article presents a signal-power integrated GD for MV SiC MOSFETs with a compact footprint. The proposed GD transmits both the pulsewidth modulation (PWM) signal and GD power by 20-MHz modulated class-E resonant flyback converters, where the transmitted GD power can maintain constant within the full PWM duty-cycle range (i.e., 0%-100%). In addition, the PWM signal transmission of the proposed GD achieves a low total propagation delay time < 75 ns by utilizing the fast transient of 20-MHz RFCs and the edge-based envelope detector. A printed-circuit-board-based coreless transformer is integrated into the proposed GD to achieve an insulation voltage higher than 10 kV RMS and a low coupling capacitance of 5.85 pF. The commonmode transient immunity of proposed GD is higher than 100 V/ns, which is beneficial to drive MV SiC MOSFETs with high dv/dt. The proposed GD does not require additional GDPSs nor fiber-optics, which achieves a smaller size compared to conventional isolated GDs and is promising to be integrated into SiC MOSFET module packages. Experimental results on 3.3 kV and 10 kV SiC MOSFETs are provided to validate the effectiveness of the proposed GD. Index Terms-Common-mode transient immunity (CMTI), gate driver (GD), medium-voltage (MV) SiC MOSFETs, MHz-pulsetransformer, signal-power integrated transmission. I. INTRODUCTIONM EDIUM-VOLTAGE (MV) SiC MOSFETs, which span 2.5 to 15 kV range, have attracted the increased attention recently [1]- [3]. Due to the high blocking voltage, fast switching speed, low switching loss, and high-temperature endurability, newly emerged MV SiC MOSFETs have a great potential to improve the efficiency and power density of MV converters and drive down the system complexity [4], [5]. On the other hand, the isolated gate driver (GD) is required to provide the sufficient galvanic isolation and high common-mode transient immunity (CMTI) for MV SiC MOSFET applications [6].

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A Robust 10 kV SiC MOSFET Gate Driver with Fast Overcurrent Protection Demonstrated in a MMC Submodule

Cited by 11 publications

References 15 publications

Comprehensive Analysis and Improvement Methods of Noise Immunity of Desat Protection for High Voltage SiC MOSFETs With High DV/DT

Comprehensive Analysis and Improvement Methods of Noise Immunity of Desat Protection for High Voltage SiC MOSFETs With High DV/DT

A short circuit protection circuit for SiC MOSFET with self-adjustive blanking time

A MHz-Pulse-Transformer Isolated Gate Driver With Signal-Power Integrated Transmission for Medium-Voltage SiC MOSFETs

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