A Robust Approach for Process Variation Aware Mask Optimization

Kuang, Jian; Chow, Wing-Kai; Young, Evangeline F. Y.

doi:10.7873/date.2015.1045

Cited by 31 publications

(26 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, it has a relatively large PV band area. Algorithm in [16] outperforms the overall score of the algorithm published in [35] by 9%. Additionally, it is 2.5 times faster.…”

Section: Comparison With Recent Algorithmsmentioning

confidence: 99%

“…However, complex masks are outputted from this algorithm. A robust approach for process variation OPC has been recently published in [35] at the cost of outputting complex masks.…”

Section: Recent Researchmentioning

confidence: 99%

“…Exploiting intensity difference map concept is the main reason, which turns out into minimizing the number of kernels needed for simulation during optimization. To verify the effectiveness of the proposed OPC algorithm from mask manufacturability perspective, the algorithm published in [35] and the proposed algorithm in [16] have been compared in terms of mask notch and spacing rule violations, in addition to the mask data volume. Table 2 shows this comparison, in which pattern fidelity, process variability, and computation time are included.…”

Section: Comparison With Recent Algorithmsmentioning

confidence: 99%

“…As shown Table 2, the algorithm in [35] effectively tackles pattern fidelity under nominal process condition. However, it has a relatively large PV band area.…”

Section: Comparison With Recent Algorithmsmentioning

confidence: 99%

See 3 more Smart Citations

Optical Proximity Correction (OPC) Under Immersion Lithography

Ahmed¹,

Takahashi²,

Kodaman³

2018

Micro/Nanolithography - A Heuristic Aspect on the Enduring Technology

View full text Add to dashboard Cite

As advanced technology nodes continue scaling down into sub-16 nm regime, optical microlithography becomes more vulnerable to process variations. As a result, overall lithographic yield continuously degrades. Since next-generation lithography (NGL) is still not mature enough, the industry relies heavily on resolution enhancement techniques (RETs), wherein optical proximity correction (OPC) with 193 nm immersion lithography is dominant in the foreseeable future. However, OPC algorithms are getting more aggressive. Consequently, complex mask solutions are outputted. Furthermore, this results in long computation time along with mask data volume explosion. In this chapter, recent state-of-the-art OPC algorithms are discussed. Thereafter, the performance of a recently published fast OPC methodology-to generate highly manufactured mask solutions with acceptable pattern fidelity under process variations-is verified on the public benchmarks.

show abstract

“…However, it has a relatively large PV band area. Algorithm in [16] outperforms the overall score of the algorithm published in [35] by 9%. Additionally, it is 2.5 times faster.…”

Section: Comparison With Recent Algorithmsmentioning

confidence: 99%

“…However, complex masks are outputted from this algorithm. A robust approach for process variation OPC has been recently published in [35] at the cost of outputting complex masks.…”

Section: Recent Researchmentioning

confidence: 99%

Section: Comparison With Recent Algorithmsmentioning

confidence: 99%

“…As shown Table 2, the algorithm in [35] effectively tackles pattern fidelity under nominal process condition. However, it has a relatively large PV band area.…”

Section: Comparison With Recent Algorithmsmentioning

confidence: 99%

See 2 more Smart Citations

Optical Proximity Correction (OPC) Under Immersion Lithography

Ahmed¹,

Takahashi²,

Kodaman³

2018

Micro/Nanolithography - A Heuristic Aspect on the Enduring Technology

View full text Add to dashboard Cite

show abstract

“…VLSI layout patterns are significant resources for flows of various design for manufacturability (DFM) research, such as optical proximity correction (OPC) [7,10,13,15,26], layout hotspot detection [5,27,30,33,34], pattern matching [4], lithography simulation [16,17,31] and so on. However, VLSI layout pattern libraries are very often not available for research or testing due to the long and iterative technology life cycle, especially in the initial stage, which may slow down the technology node development [10].…”

Section: Introductionmentioning

confidence: 99%