Triple Patterning Lithography (TPL) is widely recognized as a promising solution for 14/10nm technology node. In this paper, we propose an efficient layout decomposition approach for TPL, with the objective to minimize the number of conflicts and stitches. Based on our analysis of actual benchmarks, we found that the whole layout can be reduced into several types of small feature clusters, by some simplification methods, and the small clusters can be solved very efficiently. We also present a new stitch finding algorithm to find all possible legal stitch positions in TPL. Experimental results show that the proposed approach is very effective in practice, which can achieve significant reduction of manufacturing cost, compared to the previous work.

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