A robust, low power, high speed voltage level shifter with built-in short circuit current reduction

Ali, Shafqat; Tanner, Steve; Farine, Pierre André

doi:10.1109/ecctd.2011.6043302

Cited by 13 publications

(4 citation statements)

References 3 publications

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“…Previous works on high-speed level-shifter report low power circuits and built-in short circuit protections but only low voltage operations [13]- [14]. Other works [15]- [16] report high-speed high-voltage level-shifters but additional high-voltage devices are required and no built-in current protection are implemented.…”

Section: Introductionmentioning

confidence: 93%

Monolithically integrated voltage level shifter for Wide Bandgap Devices-based converters

Grezaud

Ayel

Rouger

et al. 2014

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Power converters based on Wide Bandgap Devices (WBD) are able to operate at high-frequency and high-voltage. In such synchronous converters a very short dead-time is advised because a lot of WBD do no have a parasitic body diode to conduct current in reverse. Into a high-voltage inverter, isolators generate isolated floating gate signals from logic level input signals. Mismatch between high-side and low-side signal propagation delays involves setting a long secure dead-time. To overcome this matching issue in order to guarantee the dead-time duration and time location, we propose other input signal propagation paths. Both input signals pass through a single lowside 2-channel digital isolator and one isolated signal is translated to the high-side gate driver by a high-speed monolithically integrated level-shifter. The proposed voltage level translator structure has been implemented with a high-voltage diode-less SiC vertical JFET and low voltage MOSFETs. At 240V power supply voltage and 100 kHz switching frequency, the level-shifter propagation delay is only 10 ns with a 1.85 mA supply current. Moreover an effective built-in current regulator prevents the circuit from any current spikes, overvoltage and overconsumption. Such topology allows to safely set a very short 23 ns dead-time and improves WBD-based converter operations while reducing size and price.

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Section: Introductionmentioning

confidence: 93%

Monolithically integrated voltage level shifter for Wide Bandgap Devices-based converters

Grezaud

Ayel

Rouger

et al. 2014

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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“…To limit the short-circuit current in the level shifter, transistors M30-M31 were added. A similar topology, with different input transistor arrangement, and its detailed description are presented in [9]. The last block of the designed analog comparator is a JK latch circuit.…”

Section: B Analog Comparator With Hysteresismentioning

confidence: 99%

Low-Power CMOS Frequency Comparator

Kovac

Potocny

Arbet

et al. 2023

2023 46th MIPRO ICT and Electronics Convention (MIPRO)

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This paper is focused on the design and analysis of a fully on-chip frequency comparator (FC) implemented in 65 nm CMOS technology. The proposed FC employs a digital pre-processing stage followed by a rail-to-rail input and output (RRIO) voltage comparator, with low power consumption in units of µW. Evaluation accuracy is maintained for input frequencies up to 1 MHz. The FC is designed for the supply voltage of 1.2 V. The FC accepts signals with independent duty cycles and delays, without any correlation between the signals, making it an universal building block of more complex integrated systems. Presented simulation results show robustness of the proposed topology over process, temperature and supply voltage variations (PVT). The presented FC was used in complex ultra-low power System on-Chip (SoC).

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“…2) The MPMAB-based clock tree requires voltage level-up/down shifters [7]. As described in [5] Table I, the original clock skew in Mode 4 is 3.10 ns.…”

Section: Observations and Motivationmentioning

confidence: 99%

Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs

Chou

Yeh

Huang

et al. 2016

IEEE Trans. VLSI Syst.

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In a multipower-mode design, as the range of the supply voltage becomes wide, a large clock skew may occur among different power domains. To remove this clock skew, conventional power-modeaware buffers (PMABs) require a large overhead on power consumption. In this brief, we propose a new PMAB architecture for wide-voltage-range multipower-mode designs. The proposed PMAB architecture is composed of two serially connected sub-PMABs at two different voltage levels, respectively. In the front sub-PMAB, the low voltage level is used for coarse-grained clock skew minimization. In the back sub-PMAB, the high voltage level is used for fine-grained clock skew minimization. Benchmark data show that the proposed approach can effectively eliminate the clock skew with small power consumption.

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A robust, low power, high speed voltage level shifter with built-in short circuit current reduction

Cited by 13 publications

References 3 publications

Monolithically integrated voltage level shifter for Wide Bandgap Devices-based converters

Monolithically integrated voltage level shifter for Wide Bandgap Devices-based converters

Low-Power CMOS Frequency Comparator

Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs

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