A Robust Methodology for Performance Analysis on Hybrid Embedded Multicore Architectures

Abstract

Today's vehicles increasingly embed software intelligence in order to be safer for the driver, and to achieve autonomous driving in a close future. To answer the computational needs of these algorithms, system-on-chip (SoC) suppliers propose heterogeneous architectures. With such complex SoCs, embedding applications in vehicle becomes more and more complex for car manufacturers. Indeed, it is not trivial to find the best suited SoC for a given application, and to define load balancing strategies when working with heterogeneous architectures. These difficulties can be overcome by using performance prediction, based on computing architectures models. To build these models, we provide a set of test vectors which automatically extract key characteristics of tested architectures. Our methodology is able to perform a complete computing architecture model, by using 3 different levels of tests, each one characterizing a specific situation representative of real applications. We aim to obtain performance prediction for different applications, for any embedded SoCs based on models performed with this methodology. In this paper, we describe our characterization methodology, and show results obtained with embedded SoCs used for automotive applications.

A novel global methodology to analyze the embeddability of real-time image processing algorithms

“…Thus, the second level overcomes these limitations by using a generic test vector set which automatically extracts parameters, for any architectures and compilers in order to build a more precise model for the association architecture compiler. In order to extract these data, we have developed a set of generic test vectors, as described in [32].…”