A robust QR-based detector for V-BLAST and its efficient hardware implementation

Abstract

Abstract:The use of multiple antennas at both transmitting and receiving sides of communication channel has increased the spectral efficiency to near the Shannon bound. However algorithmic complexity in the realization of the receiver is a major problem for its hardware implementation. In this paper we investigate a near optimal algorithm for V-BLAST detection in MIMO wireless communication systems based on QR factorization, offering remarkable reduction in the hardware complexity.Specifically, we analyze some hardware implementation aspects of the selected algorithm through MATLAB simulations and demonstrate its robustness. This technique can be used in an efficient fixed point VLSI implementation of the algorithm.

VLSI hardware design of QR-factorizer for a V-BLAST detector

“…The angle information generated by the vectorizer is represented in micro-rotations format [2] and is saved in the dual port RAM angle memory. The angle memory will be used later by the received vector processor unit of V-BLAST detector.…”

“…However, its complex receiver makes it unsuitable for the low-power VLSI implementation. To reduce the complexity of the V-BLAST detection, several alternative algorithms, and architectures have been proposed to date [2,3,4].…”

“…At the algorithmic level the numerical stability and robustness should be considered [2,5]. At the arithmetic level signal quantization is important [2,5].…”

“…At the algorithmic level the numerical stability and robustness should be considered [2,5]. At the arithmetic level signal quantization is important [2,5]. At the architectural level parallelism and pipelining require attention [2,5].…”

“…At the arithmetic level signal quantization is important [2,5]. At the architectural level parallelism and pipelining require attention [2,5]. This paper proposes a new CORDIC based [6] hardware architecture for the QR-factorization, as the computation core for the V-BLAST detector.…”