A Satisfiability Approach to Speed Assignment for Distributed Real-Time Systems

Kumar, Pratyush; Chokshi, Devesh B.; Thiele, Lothar

doi:10.7873/date.2013.160

Cited by 4 publications

(6 citation statements)

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“…In this section we present a succinct summary of the integral parts of our SMT-based system synthesis implementation. We start with introducing state-of-the-art classical SMTbased system synthesis, which is similar to work presented in [5][6][7]9,10]. Then, we sketch the obstacles that motivated us to integrate our extensions in order to realize our proposed coordinated synthesis approach.…”

Section: Coordinated Smt-based Synthesis Approach: Motivation and Det...mentioning

confidence: 99%

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Improving Symbolic System-Level Synthesis by Solver Coordination and Domain-Specific Heuristics

Haubelt

Rausch

2022

Electronics

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Deciding binding, routing, and scheduling within system synthesis for hard real-time systems can be a challenging task. Symbolic methods leveraging results from the area of satisfiability modulo theories (SMT) solving have shown to be scalable methods for this by splitting the work between a logic solver for routing and binding, and a background theory solver performing schedulability analysis. For these methods, in order to prune the search space of infeasible implementations efficiently, a feedback by the background theory is required. It can be observed that previous approaches might fail here as feedback cannot be derived within a reasonable amount of time. We propose a coordinated synthesis approach that overcomes this issue. Here, we leverage an answer set solver as logic solver that is enhanced with a scheduling-aware binding and routing refinement. Based on the answer set solver’s decisions for binding and routing, a background theory solver then computes time-triggered schedules to resolve resource access conflicts. If no feasible schedule exists, a feedback to the answer set solver can be derived within reasonable time. Our experiments synthesizing massively parallel hardware architectures show that our approach increases the applicability of symbolic synthesis considerably. While more than half of the investigated instances in our experiments cannot be solved in the non-coordinated approach already at small 2-dimensional 3×3 tiled mesh hardware architectures with 60% average computational utilization per tile, the coordinated synthesis approach scales up to 5×5 architectures with average utilization of 70% per tile (2.8× the hardware architecture size than before). Furthermore, we increase the scalability and the robustness of our approach by encoding our domain-knowledge within domain-specific heuristics in our designated answer set solver. Within our experiments, we observe that the domain-specific heuristics enable us to scale up to 6×6 architectures with 70% average utilization per tile.

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Section: Coordinated Smt-based Synthesis Approach: Motivation and Det...mentioning

confidence: 99%

“…Kumar et al [10] build on the same T -solver like [5,6] but also consider delay, buffer and energy constraints of incomplete models. By using incomplete models, the variables of bindings and multi-hop routings proposed to the T -solver are only partially assigned other than required by the system specification.…”

Section: Related Workmentioning

confidence: 99%

Improving Symbolic System-Level Synthesis by Solver Coordination and Domain-Specific Heuristics

Haubelt

Rausch

2022

Electronics

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“…Through a special SAT solver extension enhanced with real-time scheduling theory, the proposed approach is guaranteed to find an optimal allocation for realistic task systems. In [19], authors studied the problem of assigning speeds to resources serving distributed applications with delay, buffer and energy constraints. They proposed a approach by coupling a SAT solver with the background theory of Real-Time Calculus (RTC).…”

Section: Scheduling Based On Sat and Smtmentioning

confidence: 99%

“…We need to decrease the setting value of sepu. We use binary search to find the maximum value of sepu (line [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. With the maximum value of sepu, a solution model can be returned by function CallSMTSolver(A).…”

Section: Schedule Synthesismentioning

confidence: 99%

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SMT-Based Scheduling for Overloaded Real-Time Systems

Zhuo

Hai-tao

Tan

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYIn a real-time system, tasks are required to be completed before their deadlines. Under normal workload conditions, a scheduler with a proper scheduling policy can make all the tasks meet their deadlines. However, in practical environment, system workload may vary widely. Once system workload becomes too heavy, so that there does not exist a feasible schedule can make all the tasks meet their deadlines, we say the system is overloaded under which some tasks will miss their deadlines. To alleviate the degrees of system performance degradation caused by the missed deadline tasks, the design of scheduling is crucial. Many design objectives can be considered. In this paper, we first focus on maximizing the total number of tasks that can be completed before their deadlines. A scheduling method based on satisfiability modulo theories (SMT) is proposed. In the method, the problem of scheduling is treated as a satisfiability problem. The key work is to formalize the satisfiability problem using firstorder language. After the formalization, a SMT solver (e.g., Z3, Yices) is employed to solve this satisfiability problem. An optimal schedule can be generated based on the solution model returned by the SMT solver. The correctness of this method and the optimality of the generated schedule can be verified in a straightforward manner. The time efficiency of the proposed method is demonstrated through various simulations. Moreover, in the proposed SMT-based scheduling method, we define the scheduling constraints as system constraints and target constraints. This means if we want to design scheduling to achieve other objectives, only the target constraints need to be modified. To demonstrate this advantage, we adapt the SMT-based scheduling method to other design objectives: maximizing effective processor utilization and maximizing obtained values of completed tasks. Only very little changes are needed in the adaption procedure, which means the proposed SMT-based scheduling method is flexible and sufficiently general.

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