A scalability Study of Columbia using the NAS Parallel Benchmarks

Saini, Subhash; Chang, Junghwan; Hood, Robert; Jin, Haoqiang

doi:10.12921/cmst.2006.si.01.33-45

Cited by 7 publications

(3 citation statements)

References 4 publications

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“…Furthermore, they also show that performance of some irregular scientific applications can decrease for more than 8 threads. Similar observations were made by Saini et al [32] for a different machine.…”

Section: Related Worksupporting

confidence: 90%

Feedback-driven threading

Aater

QureshiMoinuddin

PattYale

2008

SIGARCH Comput. Archit. News

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Extracting high-performance from the emerging Chip Multiprocessors (CMPs) requires that the application be divided into multiple threads. Each thread executes on a separate core thereby increasing concurrency and improving performance. As the number of cores on a CMP continues to increase, the performance of some multi-threaded applications will benefit from the increased number of threads, whereas, the performance of other multi-threaded applications will become limited by data-synchronization and off-chip bandwidth. For applications that get limited by datasynchronization, increasing the number of threads significantly degrades performance and increases on-chip power. Similarly, for applications that get limited by off-chip bandwidth, increasing the number of threads increases on-chip power without providing any performance improvement. Furthermore, whether an application gets limited by data-synchronization, or bandwidth, or neither depends not only on the application but also on the input set and the machine configuration. Therefore, controlling the number of threads based on the run-time behavior of the application can significantly improve performance and reduce power.This paper proposes Feedback-Driven Threading (FDT), a framework to dynamically control the number of threads using runtime information. FDT can be used to implement Synchronization-Aware Threading (SAT), which predicts the optimal number of threads depending on the amount of data-synchronization. Our evaluation shows that SAT can reduce both execution time and power by up to 66% and 78% respectively. Similarly, FDT can be used to implement Bandwidth-Aware Threading (BAT), which predicts the minimum number of threads required to saturate the offchip bus. Our evaluation shows that BAT reduces on-chip power by up to 78%. When SAT and BAT are combined, the average execution time reduces by 17% and power reduces by 59%. The proposed techniques leverage existing performance counters and require minimal support from the threading library.

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Section: Related Worksupporting

confidence: 90%

Feedback-driven threading

Aater

QureshiMoinuddin

PattYale

2008

SIGARCH Comput. Archit. News

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“…There is a large body of prior work that studied the scalability of the NPB on high-performance computing systems. To name just a few, Ramachandran et al presented a study of NPB on the KSR-1 machine in [12], Wong et al presented a study of the NPB on an SGI Origin 2000 machine in [13], and Saini et al study the scalability of the NPB on NASA's Columbia system in [14]. These and other works mostly focused on understanding the strong scaling of the NPB on existing systems.…”

Section: Related Workmentioning

confidence: 99%

Extending the BT NAS Parallel Benchmark to exascale computing

Wijngaart

Sridharan

Lee

2012

2012 International Conference for High Performance Computing, Networking, Storage and Analysis

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The NAS Parallel Benchmarks (NPB) are a wellknown suite of benchmarks that proxy scientific computing applications. They specify several problem sizes that represent how such applications may run on different sizes of HPC systems. However, even the largest problem (class F) is still far too small to exercise properly a petascale supercomputer. Our work shows how one may scale the Block Tridiagonal (BT) NPB from today's published size to petascale and exascale computing systems. In this paper we discuss the pros and cons of various ways of scaling. We discuss how scaling BT would impact computation, memory access, and communications, and highlight the expected bottleneck, which turns out to be not memory or communication bandwidth, but network latency. Two complementary ways are presented to overcome latency obstacles. We also describe a practical method to gather approximate performance data for BT at exascale on actual hardware, without requiring an exascale system.

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“…This common behaviour [28][29][30]32] can be attributed to essentially two independent effects. First, on any given system off-chip memory bandwidth is limited, and some number of actively working cores is bound to saturate it.…”

Section: Introductionmentioning

confidence: 99%

Resource-Aware Data Parallel Array Processing

Grelck

Blom

2020

Int J Parallel Prog

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Malleable applications may run with varying numbers of threads, and thus on varying numbers of cores, while the precise number of threads is irrelevant for the program logic. Malleability is a common property in data-parallel array processing. With ever growing core counts we are increasingly faced with the problem of how to choose the best number of threads. We propose a compiler-directed, almost automatic tuning approach for the functional array processing language SaC. Our approach consists of an offline training phase during which compiler-instrumented application code systematically explores the design space and accumulates a persistent database of profiling data. When generating production code our compiler consults this database and augments each data-parallel operation with a recommendation table. Based on these recommendation tables the runtime system chooses the number of threads individually for each data-parallel operation. With energy/power efficiency becoming an ever greater concern, we explicitly distinguish between two application scenarios: aiming at best possible performance or aiming at a beneficial trade-off between performance and resource investment.

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A scalability Study of Columbia using the NAS Parallel Benchmarks

Abstract: Not many fully integrated Grid solutions exist on today's market. In this paper we present the PSNC's Grid toolkit, called Gridge, which is fully integrated Grid environment, consisting of tools and Grid services to enable challenging scientific and commercial applications on the Grid.

Cited by 7 publications

References 4 publications

Feedback-driven threading

Feedback-driven threading

Extending the BT NAS Parallel Benchmark to exascale computing

Resource-Aware Data Parallel Array Processing

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