Feedback-driven threading

115

Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the singleand multi-core performance of streaming kernels. The model refines the well-known roofline model, since it can predict the scaling and the saturation behavior of bandwidth-limited loop kernels on a multicore chip. The saturation point is especially relevant for considerations of energy consumption. From power dissipation measurements of benchmark programs with vastly different requirements to the hardware, we derive a simple, phenomenological power model for the Sandy Bridge processor. Together with the ECM model, we are able to explain many peculiarities in the performance and power behavior of multicore processors, and derive guidelines for energy-efficient execution of parallel programs. Finally, we show that the ECM and power models can be successfully used to describe the scaling and power behavior of a lattice-Boltzmann flow solver code.

Section: The Ecm Model: Multicore Scalingmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Exploring performance and power properties of modern multi‐core chips via simple machine models

Hager¹,

Treibig²,

Habich³

et al. 2013

115

“…This lack of scalability is related to different software and hardware issues, such as data-synchronization, concurrent shared-memory accesses, off-chip bus saturation, and functional unit saturation. [2][3][4][5] Accordingly, different dynamic concurrency throttling (DCT) strategies have been proposed to decrease the number of executing threads of a parallel application according to its available scalability, making better use of hardware resources and reducing costs. 3,4,[6][7][8][9][10] Therefore, when DCT is applied to a given application with limited scalability, the number of active threads will likely be less than the number of available cores in the system.…”

Section: Introductionmentioning

confidence: 99%

“…[2][3][4][5] Accordingly, different dynamic concurrency throttling (DCT) strategies have been proposed to decrease the number of executing threads of a parallel application according to its available scalability, making better use of hardware resources and reducing costs. 3,4,[6][7][8][9][10] Therefore, when DCT is applied to a given application with limited scalability, the number of active threads will likely be less than the number of available cores in the system. In this scenario, the system will be underutilized, that is, cores and cache memories not being used by the application will be idle.…”

Section: Introductionmentioning

confidence: 99%

Smart resource allocation of concurrent execution of parallel applications

Silva

Nogueira

Lima

et al. 2021

Thread‐level parallelism (TLP) has been widely exploited to optimize computational resource usage in high‐performance systems. However, as many applications do not scale as the number of threads increase, resources will be wasted when the application executes with the maximum possible number of threads (i.e., the default execution) rather than fewer threads (thread throttling) that may use the resources more efficiently. Hence, instead of executing only one application with as many threads as possible, one can run more applications simultaneously by applying thread throttling to each one. The primary outcome of this strategy is a significant reduction in the total execution time and energy consumption when the system needs to execute a list of applications. Given that, we propose a smart resource allocation (SRA) for concurrent parallel application execution. It automatically finds the ideal degree of TLP for each application and guides the simultaneous parallel applications execution. When running 25 well‐known benchmarks on three multicore systems and comparing SRA to state‐of‐the‐art strategies (e.g., Batch, Equal policy, and Scalability), SRA improves the EDP by 87.4% over the Batch strategy; 75.5% over the Equal policy; and 38.8% over the scalability strategy.

Chip‐level and multi‐node analysis of energy‐optimized lattice Boltzmann CFD simulations

Wittmann¹,

Hager²,

Zeiser³

et al. 2015

Memory-bound algorithms show complex performance and energy consumption behavior on multicore processors. We choose the lattice Boltzmann method on an Intel Sandy Bridge cluster as a prototype scenario to investigate if and how single-chip performance and power characteristics can be generalized to the highly parallel case. First, we perform an analysis of a sparse-lattice lattice Boltzmann method implementation for complex geometries. Using a single-core performance model, we predict the intra-chip saturation characteristics and the optimal operating point in terms of energy-to-solution as a function of implementation details, clock frequency, vectorization, and number of active cores per chip. We show that high single-core performance and a correct choice of the number of active cores per chip are the essential optimizations for the lowest energy-to-solution at minimal performance degradation. Then we extrapolate to the Message Passing Interface (MPI)-parallel level and quantify the energy-saving potential of various optimizations and execution modes, where we find these guidelines to be even more important, especially when communication overhead is non-negligible. In our setup, we could achieve energy savings of 35% in this case, compared with a naive approach. We also demonstrate that a simple non-reflective reduction of the clock speed leaves most of the energy-saving potential unused.[1-10]. Here, we conduct a thorough analysis of performance and energy-to-solution on the chip and highly parallel levels for an MPI-parallel implementation of LBM. We start from observations of the intra-chip saturation characteristics of two different implementations, which differ in the order in which the flow data in the lattice sites are updated ('propagation methods' [10]). Then we apply the execution-cache-memory (ECM) performance model and a simple multicore power model to describe the optimal operating point in terms of performance and energy-to-solution as a function of the clock frequency and the single instruction multiple data (SIMD) vectorization. To find out whether the knowledge thus gained at the chip level can be generalized to the highly parallel case, we conduct scaling experiments on a modern cluster system up to a point where MPI communication overhead becomes significant.This paper is organized as follows. The remainder of Section 1 covers related work, the basics of the lattice Boltzmann implementations, the hardware used for testing, and a list of contributions. Section 2 then introduces, applies, and validates the ECM model on the Intel Sandy Bridge architecture. In Section 3, we use a recently introduced multicore power model to identify the optimal operating points on the chip. Finally, Section 4 presents performance data for highly parallel runs and analyzes the impact of the different parameters (clock speed, number of cores per chip, SIMD vectorization, and system baseline power). Section 5 gives a summary and an outlook to future research. Related workThe roofline model of Williams et al. [11] pr...