A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

Jeon, Sanggeun; Wang, Yu-Jiu; Wang, Hua; Bohn, Florian; Natarajan, Arun; Babakhani, Aydin; Hajimiri, Ali

doi:10.1109/jssc.2008.2004863

Cited by 82 publications

(32 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Phase shifters in the phased array adjust the phase between elements in order to coherently combine the elements' output signals, which leads to an RF output with higher power than a single element. In addition, interference signals arriving in the array with different incident angles are nulled according to the array pattern [7]. However, if output signals from each element are not summed coherently, the desired signal will be significantly attenuated,, while the undesired signals will be amplified, thus degrading the SNR.…”

Section: Phased Arrays : Overview and Challengementioning

confidence: 99%

See 1 more Smart Citation

A self-compensating built-in self-test solution for RF phased array mismatch

Jeong

Kitchen

Ozev

2015

2015 IEEE International Test Conference (ITC)

View full text Add to dashboard Cite

An RF Phased array can steer the direction of the beam electronically and it brings about benefits in terms of signal to noise ratio (SNR) and directivity. However, testing the phased array generally requires expensive and high performance RF equipment. This increases production test cost and hampers in-field calibration. We present a low-cost, self-compensating Built-In Self-test (BIST) and calibration solution for RF phased arrays. In our proposed method, we apply a sinusoidal test signal with unknown amplitude to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. The BIST circuits are designed and post layout simulations are performed with within-die and die-to-die process variations. Simulations confirm that the BIST circuit provides very accurate results without having to know sinusoidal signal amplitudes or the relation between them. Furthermore, a prototype four-element phased-array PCB was designed and fabricated for verifying our proposed method. With the proposed method, the phase difference between elements can be measured and calibrated with less than 1 error, which would allow for self-monitoring in 6-bit phased array applications.

show abstract

Section: Phased Arrays : Overview and Challengementioning

confidence: 99%

“…In [6], [7], the performance of the phased array is tested using an artificial wave front. The wave is generated by feeding the RF inputs to each receiver path…”

mentioning

confidence: 99%

A self-compensating built-in self-test solution for RF phased array mismatch

Jeong

Kitchen

Ozev

2015

2015 IEEE International Test Conference (ITC)

View full text Add to dashboard Cite

show abstract

“…As shown in Fig. 3, the proposed PLL is especially suitable for direct-conversion scalable phased-array TRXs with a large element number [23], which has become quite popular recently. To provide LO signals for different elements, the proposed PLL can be readily duplicated and synchronized by a low-frequency crystal as the reference.…”

Section: B Embedded Phase-shifting Scheme In Phased-array Trxsmentioning

confidence: 99%

Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

Yue

Luong

Hong

2015

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of 90/ 84 dBc/Hz at 100-kHz offset and 94/ 88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm . Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 range with an average resolution of 3.9 and amplitude variation less than 0.1 dB, which makes it suitable for phased-array transceivers. Index Terms-CMOS, frequency divider, millimeter-wave (mm-Wave), phase-locked loop (PLL), phase shifter, phased array, voltage-controlled oscillator (VCO).

show abstract

“…Growing demands for higher data rate, greater channel capacity, and more security have increased attentions to phased arrays for modern communication systems and radars [1,2]. In addition, phased arrays provide higher directivity, larger effective isotropic radiated power (EIRP) in the transmitter, and higher signal-tonoise ratio (SNR) in the receiver as compared to a single-element transceiver [3,4].…”

Section: Introductionmentioning

confidence: 99%