A Scalable and Adaptive Convolutional Neural Network Accelerator

Pidanič, Jan; Vyas, Arpan; Karki, Rishav; Vij, Prateek; Trivedi, Gaurav; Němec, Zdeněk

doi:10.1109/radioelektronika54537.2022.9764951

Cited by 2 publications

(2 citation statements)

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“…On the other hand, studies on CNN hardware acceleration architecture designs are increasing vigorously [29,[35][36][37]. Parallel processing engine (PE) and pipelined architecture are widely used in CNN accelerators to improve bandwidth and reduce latency.…”

Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%

“…However, each layer of YOLO has a custom implementation on the FPGA, which means the architecture is completely YOLO-specific and cannot accept any changes to the network. In contrast, Pidanic et al [37] proposed a scalable CNN accelerator, which can process networks of different sizes. However, the proposed accelerator can only deal with convolution, pooling, and fully connected situations, which limits the types of network it can adapt to.…”

Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%

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Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application

Yan

Zhang

et al. 2022

Remote Sensing

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In recent years, convolutional neural network (CNN)-based algorithms have been widely used in remote sensing image processing and show tremendous performance in a variety of application fields. However, large amounts of data and intensive computations make the deployment of CNN-based algorithms a challenging problem, especially for the spaceborne scenario where resources and power consumption are limited. To tackle this problem, this paper proposes an automatic CNN deployment solution on resource-limited field-programmable gate arrays (FPGAs) for spaceborne remote sensing applications. Firstly, a series of hardware-oriented optimization methods are proposed to reduce the complexity of the CNNs. Secondly, a hardware accelerator is designed. In this accelerator, a reconfigurable processing engine array with efficient convolutional computation architecture is used to accelerate CNN-based algorithms. Thirdly, to bridge the optimized CNNs and hardware accelerator, a compilation toolchain is introduced into the deployment solution. Through the automatic conversion from CNN models to hardware instructions, various networks can be deployed on hardware in real-time. Finally, we deployed an improved VGG16 network and an improved YOLOv2 network on Xilinx AC701 to evaluate the effectiveness of the proposed deployment solution. The experiments show that with only 3.407 W power consumption and 94 DSP consumption, our solution achieves 23.06 giga operations per second (GOPS) throughput in the improved VGG16 and 22.17 GOPS throughput in the improved YOLOv2. Compared to the related works, the DSP efficiency of our solution is improved by 1.3–2.7×.

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Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%

Section: Hardware Acceleration For Cnnsmentioning

confidence: 99%