A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)

Savaş, Erkay; Tenca, A.F.; Koç, Çetin Kaya

doi:10.1007/3-540-44499-8_22

Cited by 92 publications

(110 citation statements)

References 18 publications

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“…If the third operand is all zeros then the first operand is routed to the destination FU; otherwise the second operand is the one routed to the destination FU. The MUX is not needed to implement any of the AES candidates but it is necessary for the implementation of multiple-precision algorithms for the asymmetric cryptographic algorithms [20]. If-conditions are program sections that pose security vulnerabilities with respect to sidechannel attacks on control-oriented processors [1].…”

Section: Readreg Writereg Readsboxmentioning

confidence: 99%

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

Farouk

El-Hadidi

Elfarag

2012

IJNC

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The past two decades have witnessed a revolution in the use of electronic devices in our daily activities. Increasingly, such activities involve the exchange of personal and sensitive data by means of portable and light weight devices. This implied the use of security applications in devices with tight processing capability and low power budget. Current architectures for processors that run security applications are optimized for either high-performance or low energy consumption. We propose an implementation for an architecture that not only provides high performance and low energy consumption but also mitigates security attacks on the cryptographic algorithms which are running on it. The proposed architecture of the GloballyAsynchronous Locally-Synchronous-based Low Power Security Processor (GALS-based LPSP) inherits the scheduling freedom and high performance from the dataflow architectures and the low energy consumption and flexibility from the GALS systems. In this paper, a prototype of the GALS-based LPSP is implemented as a soft core on the Virtex-5 (xc5-vlx155t) FPGA. The architectural features that allow the processor to mitigate Side-Channel attacks are explained in detail and tested on the current encryption standard, the AES. The performance analysis reveals that the GALS-based LPSP achieves two times higher throughput with one and a half times less energy consumption than the currently used embedded processors.

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Section: Readreg Writereg Readsboxmentioning

confidence: 99%

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

Farouk

El-Hadidi

Elfarag

2012

IJNC

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“…the ability to process operands of any size without the need to modify or re-design a given implementation [19]. The ECAU contains a 192-bit multiplier that can be used for any binary extension field GF(2 m ) of degree up to 192, e.g.…”

Section: Improvements Over Previous Workmentioning

confidence: 99%

“…This means that our system is limited scalable similar to the cryptographic processor described in [9], but does not provide the high scalability of the ECC hardware from [19]. We emphasize that attaining scalability in hardware/software co-design affects all abstraction levels and layers between hardware and software (including the operand transfers), and is not a "pure" hardware design issue as in [19]. For instance, when 1 Batina et al presented a hyperelliptic curve cryptosystem of genus 2 over the field GF(2 83 ).…”

Section: Improvements Over Previous Workmentioning

confidence: 99%

Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller

Koschuch

Lechner

Weitzer

et al. 2006

Lecture Notes in Computer Science

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Abstract. 8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. The performance of 8-bit microcontrollers is often too poor for the implementation of public-key cryptography in software. In this paper we present a minimalist hardware accelerator for enabling elliptic curve cryptography (ECC) on an 8051 microcontroller. We demonstrate the importance of removing system-level performance bottlenecks caused by the transfer of operands between hardware accelerator and external RAM. The integration of a small direct memory access (DMA) unit proves vital to exploit the full potential of the hardware accelerator. Our design allows to perform a scalar multiplication over the binary extension field GF(2 191 ) in 118 msec at a clock frequency of 12 MHz. Considering performance and hardware cost, our system compares favorably with previous work on similar 8-bit platforms.

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“…Alternatives are heavy-weight accelerators for complete EC operations [4,5,7,8] or hardware-software co-design approaches where com-putational intensive tasks are done by an EC coprocessor [9]. These coprocessors can either calculate all finite field operations [12] or support only multiplication as the most demanding finite field operation [10,11]. Circuits for calculating the multiplicative inverse in the finite fields GF(p) and GF(2 m ) are rare [12,13].…”

Section: Related Workmentioning

confidence: 99%

“…Even than, exponentiation takes more than 100 times longer than multiplication which makes the use of affine coordinates for EC operations unattractive. Useful multipliers which can operate both in GF(p) and GF(2 m ) were presented by J. Großschädl [11] and E. Savaş et al [10]. J. Großschädl's approach uses a dual-field bit-serial multiplier utilizing interleaved modular reduction.…”

Section: Related Workmentioning

confidence: 99%

A Low-Cost ECC Coprocessor for Smartcards

Aigner¹,

Bock

Hütter

et al. 2004

Lecture Notes in Computer Science

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Abstract. In this article we present a low-cost coprocessor for smartcards which supports all necessary mathematical operations for a fast calculation of the Elliptic Curve Digital Signature Algorithm (ECDSA) based on the finite field GF(2 m ). These ECDSA operations are GF(2 m ) addition, 4-bit digit-serial multiplication in GF(2 m ), inversion in GF(2 m ), and inversion in GF(p). An efficient implementation of the multiplicative inversion which breaks the 11:1 limit regarding multiplications makes it possible to use affine instead of projective coordinates for point operations on elliptic curves. A bitslice architecture allows an easy adaptation for different bit lengths. A small chip area is achieved by reusing the hardware registers for different operations.

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A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)

Cited by 92 publications

References 18 publications

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller

A Low-Cost ECC Coprocessor for Smartcards

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