Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller

Abstract

Abstract. 8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. The performance of 8-bit microcontrollers is often too poor for the implementation of public-key cryptography in software. In this paper we present a minimalist hardware accelerator for enabling elliptic curve cryptography (ECC) on an 8051 microcontroller. We demonstrate the importance of removing system-level performance bottlenecks caused by the transfer of operands between hardware accelerator and external RAM. The integration of a small direct memory access (DMA) unit proves vital to exploit the full potential of the hardware accelerator. Our design allows to perform a scalar multiplication over the binary extension field GF(2 191 ) in 118 msec at a clock frequency of 12 MHz. Considering performance and hardware cost, our system compares favorably with previous work on similar 8-bit platforms.

Vampire Attacks: Draining Life from Wireless Ad Hoc Sensor Networks

“…In other words, the overhead is constant (Oð1Þ) for a given network configuration (maximum path length), and cannot be influenced by an adversary. Fortunately, hardware cryptographic accelerators are increasingly common and inexpensive to compensate for increased security demands on low-power devices, which lead to increased computational load and reduced battery life [17], [18], [20], [33], [39], [46], [47], [49], [56].…”

Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security

“…3 and all the design considerations will be discussed below. The hardware/software partitioning method adopted in this design is trying to offload the field arithmetic operations from the CPU and execute them in a dedicated ECC coprocessor [13,14]. For traditional ECC coprocessor designs, all other higher level point operations, such as point addition/doubling, are implemented in software running on CPU.…”

“…To compare with other similar ECC codesigns [13,14,29,30,36,37], our proposed ECC coprocessor architecture considers optimizations for performance, flexibility and security at the same time. For performance, the designs described in [29,30], same as the base design of the ECC coprocessor architecture proposed in this paper with single ECC datapath, have already shown good tradeoffs between area and speed.…”

An Elliptic Curve Cryptography Coprocessor over GF(2m) on a Low-Cost Embedded System

“…There are numerous papers dealing with the hardware/software co-design of ECC on 8-bit CPU platforms [2,3,4,6,7,8]. The performance of ECC coprocessors in previous work highly depended on the efficiency of the platforms, in [3,6,7,8] the performance built around an AVR microcontroller is faster than that of those using 8051 [2,4].…”

“…The performance of ECC coprocessors in previous work highly depended on the efficiency of the platforms, in [3,6,7,8] the performance built around an AVR microcontroller is faster than that of those using 8051 [2,4]. What's more, it's difficult to apply them to different platforms, as the differences of instructions among platforms.…”