2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) 2018
DOI: 10.1109/newcas.2018.8585644
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A Scalable Architecture for Multi Millions Frames per Second CMOS Sensor With Digital Storage

Abstract: This paper describes a 3D Integrated Circuit (3D-IC) architecture of a burst image sensor (BIS) with embedded digitization and digital storage. This architecture also proposes a new technique to further increase both the frame rate and the stored image capacity at the cost of a spatial resolution reduction. A 2D monolithic demonstrator that takes into account the constraints of a future 3D-IC imager has been fabricated. Experimental results are presented showing that a frame rate from 5 up to 45 Mega frames pe… Show more

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Cited by 3 publications
(6 citation statements)
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“…134,150 Recently, electron-transfer-based temporal shearing has also been implemented in a streak-camera sensor. 167,168 Hundreds of sampling and storage cells are placed underneath a line of photodiodes. During the sensor's exposure, the 1D signal is sampled and sequentially stored at a temporal resolution of 500 ps.…”
Section: Temporal Shearing Unitmentioning
confidence: 99%
See 1 more Smart Citation
“…134,150 Recently, electron-transfer-based temporal shearing has also been implemented in a streak-camera sensor. 167,168 Hundreds of sampling and storage cells are placed underneath a line of photodiodes. During the sensor's exposure, the 1D signal is sampled and sequentially stored at a temporal resolution of 500 ps.…”
Section: Temporal Shearing Unitmentioning
confidence: 99%
“…213 Selecting a multifunctional component (e.g., a metalens and a TDI sensor) provides another approach to reducing the number of optical elements in CUP systems. Advances in sensor design and nanofabrication could provide the streak imaging sensor 167,168 with a 2D FOV. All efforts will contribute to engineering compact and even miniature CUP systems in the future.…”
Section: Higher Dimensionsmentioning
confidence: 99%
“…Implementing SRAM will involve partitioning issues (one cut for several pixels) and local pixel addressing considerations. For instance this SRAM partitionning has already been investigated in the context of high speed imaging [8].…”
Section: Embedded Digital Memorymentioning
confidence: 99%
“…A 3D stacked IC approach overcomes these restrictions by allowing a distribution of electronic functions on dedicated tiers [8]. Top tier photodiodes can benefit from imaging technology and backside illumination for a maximal sensitivity, while the bottom tier provide room for in-pixel memories without sacrifying the fill factor (Fig.…”
Section: Introductionmentioning
confidence: 99%
“…Several high-speed pixel front-end architectures have been reported such as CCD [7], pinned photodiodes [3], buffered and non buffered direct injection [8], Classic 4T pixel [5] or capacitive feedback transimpedance amplifiers [6], but none of these architectures offers a High Dynamic Range (HDR) feature. The HDR feature consists to capture an image with very different intensity levels without saturating.…”
Section: Introductionmentioning
confidence: 99%