A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective

Chatterjee, Subho; Rasquinha, Mitchelle; Yalamanchili, Sudhakar; Mukhopadhyay, Saibal

doi:10.1109/tvlsi.2010.2041476

Cited by 31 publications

(16 citation statements)

References 13 publications

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“…Such variation is also modeled using i.i.d. Gaussian distribution with 0.1 radian variance [7]. The nominal values and variance of the device parameters are listed in Table 3.…”

Section: Stt-ram Error Modelmentioning

confidence: 99%

“…While Chatterjee et al [7] studied the failure rate of a single STT-RAM cell using basic models for transistor and MTJ resistance, process variation effects such as RDF and geometric variation were considered in [15,28]. In this section, we also present the effects of process variation and geometric variation.…”

Section: Errors In Read and Write Operationsmentioning

confidence: 99%

“…Access transistor sizing has been investigated in [7,13], effect of process variation as well as write pulse width has been studied in [13,14,28] and voltage boosting of WL has been considered in [13,29]. Here, we also study the read reliability and investigate the effect of combination of write pulse width and voltage boosting on the write reliability.…”

Section: Circuit-level Techniques For Reducing Errormentioning

confidence: 99%

“…Many of these works focus on finding an alternative to commonly used SRAM, DRAM, and Flash memories [1,2]. The two most attractive memory technologies that have emerged are phase-change RAM (PRAM) [3,4] and spin transfer torque RAM (STT-RAM) [5][6][7]. STT-RAM is an attractive candidate for lower level caches because of its fast read and write operation, very low standby power, and high endurance.…”

Section: Introductionmentioning

confidence: 99%

“…Increasing the TMR ratio makes the separation between states wider and improves the reliability of the cell [7]. Figure 15 describes the cell structure of an STT-RAM and highlights the P and AP states.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Yang

Emre

Cao

et al. 2012

EURASIP J. Adv. Signal Process.

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Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10 -8 . For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10 -8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

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“…Such variation is also modeled using i.i.d. Gaussian distribution with 0.1 radian variance [7]. The nominal values and variance of the device parameters are listed in Table 3.…”

Section: Stt-ram Error Modelmentioning

confidence: 99%

Section: Errors In Read and Write Operationsmentioning

confidence: 99%