2016
DOI: 10.1007/978-3-319-28518-4_14
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A Scalable Flexible SOM NoC-Based Hardware Architecture

Abstract: In this paper, a parallel hardware implementation of a selforganizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware 5 × 5 SOM was validated through the FPGA implementation and its performances at a… Show more

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Cited by 8 publications
(9 citation statements)
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References 13 publications
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“…Lachmair et al ( [71]) propose a bus-interconnected multi-FPGA hardware SOM that allows the implementation of large reconfigurable networks. Abady et al propose a layered description of the HW SOM ( [72], [73]) where the computational neurons are decoupled from the communication that is implemented with a NoC. The same idea is exploited by Jovanovic et al ( [74], [75]) in a more hierarchical manner as the interconnected computational cells no longer implement neurons but clusters of neurons.…”
Section: Neuromorphic (Electronic) Architecturesmentioning
confidence: 99%
“…Lachmair et al ( [71]) propose a bus-interconnected multi-FPGA hardware SOM that allows the implementation of large reconfigurable networks. Abady et al propose a layered description of the HW SOM ( [72], [73]) where the computational neurons are decoupled from the communication that is implemented with a NoC. The same idea is exploited by Jovanovic et al ( [74], [75]) in a more hierarchical manner as the interconnected computational cells no longer implement neurons but clusters of neurons.…”
Section: Neuromorphic (Electronic) Architecturesmentioning
confidence: 99%
“…Lachmair et al ( 2013 ) propose a bus-interconnected multi-FPGA hardware SOM that allows the implementation of large reconfigurable networks. Abady et al propose a layered description of the HW SOM (Abadi et al, 2016 , 2018 ) where the computational neurons are decoupled from the communication that is implemented with a NoC. The same idea is exploited in Jovanović et al ( 2018 ) and Jovanović et al ( 2020 ) in a more hierarchical manner as the interconnected computational cells no longer implement neurons but clusters of neurons.…”
Section: State Of the Artmentioning
confidence: 99%
“…Our results are compared to three FPGA SOM implementations which are of particular interest in our case because they are all based on a NoC-based FPGA implementations [10,11,23].…”
Section: Performance Comparisonmentioning
confidence: 99%
“…The use of Euclidean distance used in the formal definition of SOM and in most of its software implementations are often replaced by a Manhattan distance [6][7][8][9][10] or Chessboard [6] distance functions to avoid multipliers and square root operators. Another common optimization is to replace the exponentiation used to compute the Gaussian neighboring function by approximations such as negative power of two implemented with shift registers [5,6,10,11] or Lookup-Tables [7,9]. In all the previously cited works, vectors are represented with integer or fixed-point arithmetic, with usually 16-bits per vector component.…”
Section: Introductionmentioning
confidence: 99%