A Scalable FPGA-Based Architecture for Depth Estimation in SLAM

Boikos, Konstantinos; Bouganis, Christos-Savvas

doi:10.1007/978-3-030-17227-5_14

Cited by 11 publications

(5 citation statements)

References 17 publications

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“…Boikos and Bouganis [43], [44], [33] have created the first complete FPGA implementation of LSD-SLAM that uses a direct approach, using a Xilinx Zynq-7020 FPGA SoC. Their design is scalable and achieved a performance of 60 FPS at a resolution of 640*480, which is on-par with a highly-optimized parallel implementation on a high-end desktop CPU, but with an order of magnitude improved power consumption.…”

Section: ) Accelerating Vo/slam Systems On Fpgasmentioning

confidence: 99%

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Exploring Sparse Visual Odometry Acceleration With High-Level Synthesis

Iordanou

Riley

et al. 2023

IEEE Access

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Visual Odometry (VO) systems are widely used to determine the position and orientation of a robot or camera in an unknown environment. They are deployed on resource-constrained platforms, such as drones and Virtual Reality (VR) or Augmented Reality (AR) headsets. VO systems harnessing modern System-on-Chip (SoCs) with integrated Field Programmable Gate Array (FPGA) have the potential to improve the overall systems performance. This paper explores the FPGA acceleration of sparse VO kernels using High-level Synthesis (HLS) as this kind of VO system has been designed to use with lowpower SoCs. We show that both computational and data transfer overheads between the processing cores of the CPU of the SoC and the accelerators on the FPGA need to be optimized to obtain better end-to-end performance. This is a result of the additional data movement incurred when using an FPGA accelerator and also because of the sparse computational nature with predictable or random memory access patterns of the kernels involved. However, state-of-the-art HLS tools are not yet able to perform the required optimizations automatically because they usually assume that the kernels to be accelerated have dense computational patterns with regular memory access. In this paper we propose three, potentially generic, methods to reduce the data transfer between the CPU and the customised hardware kernels on the FPGA; these methods are: (a) approximation based on domain-specific knowledge, (b) image compression, and (c) the use of on-the-fly computation. We present a case study of the use of these methods on SVO, a state-of-the-art sparse VO system with a semi-direct front-end. We demonstrate that our proposed methods can reduce data transfer overhead to achieve better end-to-end performance and that they can be applied not only when using standard Xilinx HLS tools but also with other state-of-the-art HLS tools, such as HeteroFlow. Compared to the baseline performance of the original SVO software on an Arm CPU, our proposed methods assist the HLS and HeteroFlow designs to achieve a speedup of 2.4x and 2.14x, respectively, without noticeable accuracy loss. The HLS and HeteroFlow designs also achieve a 1.85x and 1.89x, respectively, improvement in energy efficiency on the SoC system used. Compared to the SVO software baseline running on the Intel Xeon CPU, our proposed methods assist the HLS and HeteroFlow designs to achieve 8.2x and 8.3x improvement in energy efficiency, respectively.

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Section: ) Accelerating Vo/slam Systems On Fpgasmentioning

confidence: 99%

“…As for [32], the sparse optical flow with Lucas-Kanade method and image pyramid is used. A dense image alignment accelerator is developed using HLS in [33].…”

Section: ) Accelerating Vo/slam Systems On Fpgasmentioning

confidence: 99%

Exploring Sparse Visual Odometry Acceleration With High-Level Synthesis

Iordanou

Riley

et al. 2023

IEEE Access

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“…For instance, Rodríguez-Araujo et al [16] present a distributed FPGA-based embedded image processing system for accurate and fast simultaneous estimation of the position and orientation of remotely controlled vehicles in indoor spaces. Boikos et al [17] describe an FPGA accelerator architecture for depth estimation in SLAM algorithms achieving a rate of more than 60 mapped frames/s, similar performance to that of a high-end desktop CPU with power consumption improved by an order of magnitude.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Computing for Reactive Robotics Using Open-Source FPGAs

et al. 2021

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Reconfigurable computing provides a paradigm to create intelligent systems different from the classic software computing approach. Instead of using a processor with an instruction set, a full stack of middleware, and an application program running on top, the field-programmable gate arrays (FPGAs) integrate a cell set that can be configured in different ways. A few vendors have dominated this market with their proprietary tools, hardware devices, and boards, resulting in fragmented ecosystems with few standards and little interoperation. However, a new and complete toolchain for FPGAs with its associated open tools has recently emerged from the open-source community. Robotics is an expanding application field that may definitely benefit from this revolution, as fast speed and low power consumption are usual requirements. This paper hypothesizes that basic reactive robot behaviors may be easily designed following the reconfigurable computing approach and the state-of-the-art open FPGA toolchain. They provide new abstractions such as circuit blocks and wires for building intelligent robots. Visual programming and block libraries make such development painless and reliable. As experimental validation, two reactive behaviors have been created in a real robot involving common sensors, actuators, and in-between logic. They have been also implemented using classic software programming for comparison purposes. Results are discussed and show that the development of reactive robot behaviors using reconfigurable computing and open tools is feasible, also achieving a high degree of simplicity and reusability, and benefiting from FPGAs’ low power consumption and time-critical responsiveness.

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“…This implementation can process and track more than 22 fps with an embedded power budget and achieves a 5× speedup over [125]. Furthermore, Boikos et al [127] combine a scalable depth estimation with direct semi-dense SLAM architecture and propose a complete accelerator for semi-dense SLAM on FPGA. This architecture achieved more than 60 fps at the resolution of 640×480 and an order of magnitude power consumption improvement compared to Intel i7-4770 CPU.…”

Section: Semi-dense Slam On Fpgamentioning

confidence: 99%

A Survey of FPGA-Based Robotic Computing

Wan

Bo²,

Li³

et al. 2020

Preprint

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Recent researches on robotics have shown significant improvement, spanning from algorithms, mechanics to hardware architectures. Robotics, including manipulators, legged robots, drones, and autonomous vehicles, are now widely applied in diverse scenarios. However, the high computation and data complexity of robotic algorithms pose great challenges to its applications. On the one hand, CPU platform is flexible to handle multiple robotic tasks. GPU platform has higher computational capacities and easy-touse development frameworks, so they have been widely adopted in several applications. On the other hand, FPGA-based robotic accelerators are becoming increasingly competitive alternatives, especially in latency-critical and power-limited scenarios. With specialized designed hardware logic and algorithm kernels, FPGA-based accelerators can surpass CPU and GPU in performance and energy efficiency. In this paper, we give an overview of previous work on FPGA-based robotic accelerators covering different stages of the robotic system pipeline. An analysis of software and hardware optimization techniques and main technical issues is presented, along with some commercial and space applications, to serve as a guide for future work.

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A Scalable FPGA-Based Architecture for Depth Estimation in SLAM

Cited by 11 publications

References 17 publications

Exploring Sparse Visual Odometry Acceleration With High-Level Synthesis

Exploring Sparse Visual Odometry Acceleration With High-Level Synthesis

Reconfigurable Computing for Reactive Robotics Using Open-Source FPGAs

A Survey of FPGA-Based Robotic Computing

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