A scalable FPGA-based custom computing machine for a medical image processing

Abstract

Concentration index filter is a kind of spatial filters of images, and its typical application is diagnosis from medical images. This paper presents a dedicated computing engine for concentration index filtering. Original algorithm is modified to extract full parallelism and data width is optimized for maximizing clock speed and minimizing hardware scale. Evaluation results reveal that the system runs 100 times faster than current workstation and enables real-time diagnosis. ConcentrationIndex Filter Not small number of image processing applications suit FPGA-based hardware, as reported in many papers ([1] for example). In this paper, we focus our mind on the concentration index and present an efficient architecture of an FPGA-based system.Concentration index[2] is a characteristicmeasurement which indicates the degree of concentration of lines to a certain point in an image. For each pixel in the image, all the neighboring lines are evaluated whether they direct to the point. When the resulting concentration index scores high, it means that neighboring lines concentrate to the point. Figure 1 illustrates the calculation of concentration index at a point P. Any point Q in the neighboring area (R) of p has a line element whose length is dx and angle a. r is the length of PQ. The concentration index at the point p (we denote C(P)) is defined as follows:tational structure is rather simple. So the operation is suitable for FPGA-based systems. Thus we propose an FPGA-based concentration index operation engine with the following two features: (a) it offers sufficiently high performance and flexibility by introducing FPGA, and (b) it should be a scalable system by employing multiple FPGAs. ComplexityReduction As the number of possible patterns of line elements are eight, combinations of dx and 0. in Equation (1) are limited, and thus we can use pre-computed values of (dxlcoso.l/r) and dx/r in the equation. This reduces computational complexity considerably. ParallelismExtraction A naive algorithm derived from Equation (1) is changed to fit for hardware execution. Figure 2 shows the resulting algorithm. We can find rich parallelism in the kernel loop.

Hardware-Efficient Stochastic Binary CNN Architectures for Near-Sensor Computing

“…Point-of-Care (PoC) microscopy diagnostic support systems for different diseases (e.g., malaria, tuberculosis, and intestinal parasite infection) have been studied in detail with regard to application of deep learning. However, most of the implementations in the literature are based on conventional CPUs (Yang et al, 2020 ), high-end GPUs (Quinn et al, 2016 ), or FPGAs (Yokota et al, 2002 ; Grull et al, 2011 ). Recent work has also explored possibility of realizing such PoC systems using specialized ASIC accelerators with reduced energy consumption (Sethi et al, 2018 ).…”

A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms

“…The initial design entry is done usin design synthesis, mapping and translation ar Xilinx ISE and the simulator database is th throughput and power metrics. same amount of ge/discharge the supply voltage, ȕ is a positive mption for the by; (18) the maximum or the original (19) (20) ed for both the n can be used to (21) total capacitance nce there is no the capacitance cycle remains sample rate, the be increased to, k period of the e critical path LT original rather reduction in the allel processing, of ȕ as; ( As expected the throughput v exploit more and more concu is achieved for the 4-parall shows the latency and the clo critical path computations w Although the latency (calcu clock cycles) seems to incre period decreases with every decreases when computed in Further analysis is carried ou variations for different stru increased from 8 to 32. The c values increase as the structures urrencies.…”

Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

“…FPGAs are being increasingly used for a variety of computationally intensive applications, especially in the realm of digital signal processing (DSP) [1][2][3][4][5][6][7]. Due to rapid increases in fabrication technology, the current generation of FPGAs contains a large number of configurable logic blocks (CLBs), and are becoming more feasible for implementing a wide range of arithmetic applications.…”