Numerical techniques have long been used to compute an approximate solution of a definite integral. The traditional approaches have mostly been software oriented. However, with the current trend moving back towards hardware intensive processing, it is desirable to develop a hardware oriented solution that assesses the performance in terms of some realistic parameters such as speed, power and area. This paper aims to exploit the one-to-one correspondence that exists between the Integration algorithms and the general FIR filters. Based on this correspondence a structure is developed that implements the Integration algorithm. However, typically such implementations have large critical path delays that put a limit on the resulting sampling/throughput rates. The paper addresses this problem by exploiting concurrency at various levels within the algorithm. Pipelined and parallel structures are developed and their effects on speed and power metrics are studied separately. It is shown that by these architectural modifications the data paths within the structure can be modified and the structure can be operated at higher throughput rates and/or with lower power consumption. Because of their ability to provide a high level of hardware programmability, FPGAs have been used as the implementation platform.

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Digital Signal Processing (DSP) algorithms always have a need for calculating certain linear, trigonometric, hyperbolic, logarithmic and other transcendental functions. CORDIC based algorithms have long been used in evaluating these functions. Traditional approaches have, however, been limited to software domain only. The simplicity of operation of CORDIC algorithm encourages its implementation in hardware. In this paper a novel CORDIC architecture for sine and cosine function evaluation has been proposed. The hardware integration is carried out using Field Programmable Gate Arrays (FPGAs).The proposed algorithm is based on modified carry save addition and incorporates bit-truncation. The structure offers extremely low latency and high operating frequencies, when pipelined. The novelty of the proposed architecture is that it offers a flat timing response for varying input word lengths. The structure has an inherent capability of supporting an additional internal pipeline within each stage, enabling the structure to operate at high frequencies, typically four times that of the normal CORDIC. The performance analysis is carried out by comparing the proposed architecture against existing non-redundant (basic) and redundant (modified) architectures.