A scalable performance 32 b microprocessor

Clark, Lawrence T.; Hoffman, E.; Schaecher, Mark; Biyani, Manish; Roberts, D.; Liao, Yuan

doi:10.1109/isscc.2001.912616

Cited by 8 publications

(6 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, when used in conjunction with pulse-clocked latches in the ALU bypass loop, it is slightly faster than a domino adder, due to the elimination of one latch setup time, clock skew, and delay. Separate latches limit ALU logic switching by function to limit power dissipation [7], a technique that was used throughout the design, e.g., on the cache busses.…”

Section: B Adder and Bypass Loopmentioning

confidence: 99%

See 1 more Smart Citation

An embedded 32-b microprocessor core for low-power and high-performance applications

Clark

Hoffman

Miller

et al. 2001

IEEE J. Solid-State Circuits

Self Cite

159

View full text Add to dashboard Cite

Section: B Adder and Bypass Loopmentioning

confidence: 99%

“…A simple three-inversion one-shot circuit is used to generate the pulse [7]. The LCB is the last clock buffer level and directly drives the sequential elements.…”

Section: Clocks and Pllmentioning

confidence: 99%

An embedded 32-b microprocessor core for low-power and high-performance applications

Clark

Hoffman

Miller

et al. 2001

IEEE J. Solid-State Circuits

Self Cite

159

View full text Add to dashboard Cite

“…In applications where the operating frequency changes, dynamic voltage (and frequency) scaling (DVS) has been widely explored to minimize power dissipation [1][2][3]. The basic notion is to scale the supply voltage and stretch out the computation to the maximum available time as the processing rate is changed.…”

mentioning

confidence: 99%

A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

Miyazaki¹,

Kao²,

Chandrakasan³

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

View full text Add to dashboard Cite

Traditionally, V dd scaling has been one of the most effective ways to reduce operating power, with the device leakage component being much smaller than the dynamic switching component. In applications where the operating frequency changes, dynamic voltage (and frequency) scaling (DVS) has been widely explored to minimize power dissipation [1][2][3]. The basic notion is to scale the supply voltage and stretch out the computation to the maximum available time as the processing rate is changed. The lower limit on the supply voltage is set by the device threshold voltages, which are often sized to minimize idle mode power due to device sub-threshold leakage. Adaptive substrate biasing is also becoming common in which the circuit operates in a reduced threshold mode during active periods and switched using body bias control to a high threshold mode during inactivity [3][4]. Clearly, the minimal power point for a given performance depends not only on the power supply voltage, but also on the device threshold [5]. For a given target operating frequency, a minimal power dissipation point exists that trades off between increased subthreshold leakage currents and lower dynamic switching currents as supply (V dd ) and device thresholds (V th ) are scaled. A technique is demonstrated that minimizes power dissipation under varying processing rate requirement (i.e., workload) through the dynamic adjustment of supply (V dd ) and body bias (V bb ) in a triple-well CMOS technology. If the device thresholds are allowed to vary in addition to the supply voltage, the system achieves even lower power consumption because a lower V th corresponds to increased switching speeds.Body biasing (V bb control) is an effective technique for dynamic threshold voltage scaling [6]. In particular, forward biasing is especially important as it can increase the dynamic range of device threshold and improve circuit performance. Unfortunately, large forward V bb bias results in increased currents caused by forward-biased diodes. In this case, the optimum power point corresponds to the forward V bb where the operating speed can no longer be improved with increased forward bias.This system, shown in Figure 3.4.1a, reduces the power using adaptive control of V dd and V bb (adaptive supply voltage and body bias: ASB). Based on the incoming data and the user-set requirements (i.e., workload), a variable processor clock frequency is set using the clock generation circuit. A look-up table (LUT) translates the workload to the optimal power supply voltage for the given required using a variable voltage DC-DC converter. The LUT can also store the optimal value for the body bias. Another architecture, shown in Figure 3.4.1, is to feed the variable voltage (VAR_V dd ) to both the DSP as well as a delay locked loop (DLL) circuit that sets the body bias values for both nMOS and pMOS devices such that the required frequency is met under current operating conditions. The DLL is composed of a bodycontrolled critical-path replica, a phase detector, a decoder and a dig...

show abstract

“…Parallel clusters of multiplier, multiply-add, multiply-accumulate cores are required to perform complex filter operations in Fast Fourier Transform (FFT) accelerators while consuming ultra low energy/operation [1]. A 12x9b single-cycle two's complement twiddle multiplier for FFT acceleration implemented in 90nm dual-V t CMOS technology [2], operating at 2GHz and consuming 13.6mW at 1.3V, 110 C is presented.…”

mentioning

confidence: 99%

A 2GHz 13.6mW 12x9b multiplier for energy efficient FFT accelerators

Hsu

Venkatraman²,

Mathew³

et al.

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

View full text Add to dashboard Cite

Two's complement multipliers are performance and power-critical components for wireless baseband signal processing applications. Parallel clusters of multiplier, multiply-add, multiply-accumulate cores are required to perform complex filter operations in Fast Fourier Transform (FFT) accelerators while consuming ultra low energy/operation [1]. A 12x9b single-cycle two's complement twiddle multiplier for FFT acceleration implemented in 90nm dual-V t CMOS technology [2], operating at 2GHz and consuming 13.6mW at 1.3V, 110 C is presented. Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable this aggressive powerperformance by achieving (i) low compressor tree fanouts and wiring complexity, (ii) low active leakage power of 1.3mW and high noise tolerance with all high-V t usage, (iii) scalable multiplier performance up to 2.5GHz, 33mW at 1.7V, 110 C, and (iv) low-voltage mode multiplier performance of 35MHz, 50µW at a supply of 300mV, 110 C.

show abstract

A scalable performance 32 b microprocessor

Cited by 8 publications

References 2 publications

An embedded 32-b microprocessor core for low-power and high-performance applications

An embedded 32-b microprocessor core for low-power and high-performance applications

A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

A 2GHz 13.6mW 12x9b multiplier for energy efficient FFT accelerators

Contact Info

Product

Resources

About