A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

Abstract

Traditionally, V dd scaling has been one of the most effective ways to reduce operating power, with the device leakage component being much smaller than the dynamic switching component. In applications where the operating frequency changes, dynamic voltage (and frequency) scaling (DVS) has been widely explored to minimize power dissipation [1][2][3]. The basic notion is to scale the supply voltage and stretch out the computation to the maximum available time as the processing rate is changed. The lower limit on the supply voltage is set by the device threshold voltages, which are often sized to minimize idle mode power due to device sub-threshold leakage. Adaptive substrate biasing is also becoming common in which the circuit operates in a reduced threshold mode during active periods and switched using body bias control to a high threshold mode during inactivity [3][4]. Clearly, the minimal power point for a given performance depends not only on the power supply voltage, but also on the device threshold [5]. For a given target operating frequency, a minimal power dissipation point exists that trades off between increased subthreshold leakage currents and lower dynamic switching currents as supply (V dd ) and device thresholds (V th ) are scaled. A technique is demonstrated that minimizes power dissipation under varying processing rate requirement (i.e., workload) through the dynamic adjustment of supply (V dd ) and body bias (V bb ) in a triple-well CMOS technology. If the device thresholds are allowed to vary in addition to the supply voltage, the system achieves even lower power consumption because a lower V th corresponds to increased switching speeds.Body biasing (V bb control) is an effective technique for dynamic threshold voltage scaling [6]. In particular, forward biasing is especially important as it can increase the dynamic range of device threshold and improve circuit performance. Unfortunately, large forward V bb bias results in increased currents caused by forward-biased diodes. In this case, the optimum power point corresponds to the forward V bb where the operating speed can no longer be improved with increased forward bias.This system, shown in Figure 3.4.1a, reduces the power using adaptive control of V dd and V bb (adaptive supply voltage and body bias: ASB). Based on the incoming data and the user-set requirements (i.e., workload), a variable processor clock frequency is set using the clock generation circuit. A look-up table (LUT) translates the workload to the optimal power supply voltage for the given required using a variable voltage DC-DC converter. The LUT can also store the optimal value for the body bias. Another architecture, shown in Figure 3.4.1, is to feed the variable voltage (VAR_V dd ) to both the DSP as well as a delay locked loop (DLL) circuit that sets the body bias values for both nMOS and pMOS devices such that the required frequency is met under current operating conditions. The DLL is composed of a bodycontrolled critical-path replica, a phase detector, a decoder and a dig...

Implementing Minimum-Energy-Point Systems With Adaptive Logic

“…Both are proactive techniques, where the target is to track the delay of a real critical path with some added margin. The replica circuit can either be on the actual path [4] or it can consist of a collection of digital gates with tunable delays [5]. The latter is referred to as tunable replica circuit, and can be tuned on chip to match the delay of the critical path.…”

Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits

“…Furthermore, dynamic logic provides high-speed operation for circuits which are operating at nominal supply voltage. However, it has several disadvantages in ultra-low-voltage operation [45]. Because of the low supply level at which the output will be precharged, only a small amount of charge is stored on the dynamic node.…”

Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection

“…Previous work demonstrated that body biasing and DVFS implemented independently can achieve lower power than DVFS alone [5]. In this implementation, the processor specifies frequency and VDD while a body bias controller adjusts the body biases to meet the frequency target.…”