This paper presents a pipelined 32 bit sub-threshold adder in a 90 nm CMOS technology that combines MHzperformance with sub-pJ energy consumption. To increase variation-resilience various circuit techniques are proposed, such as sub-threshold adapted transmission gate logic, optimal sizing for noise margins and time borrowing. These techniques enable operation down to a supply of 190 mV at 10 MHz and an energy consumption of 0.4 pJ per addition. A performance of 30 MHz is obtained at a supply of 260 mV and 0.6 pJ per addition. The adder achieves an improvement in Energy-Delay Product of a factor 900 compared to the state-of-the-art sub-threshold adder design. I. INTRODUCTIONUltra-low-power digital circuits have become very important due to the high demand for wireless sensor networks and medical applications. Traditional supply voltage scaling has proven to be a valuable technique to significantly reduce energy consumption. Decreasing the supply voltage below the transistor threshold voltage can provide further energy savings. However, sub-threshold operation is often limited to very low performance and suffers severely from the ever increasing variability. Until now, the focus of sub-threshold design was mainly on minimizing energy, resulting in kHz-performance [1]. Two issues must be tackled to allow the widespread use of circuits operating in the sub-threshold region. First, the performance of circuits operating at a low supply voltage in the order of a single V t must be enhanced from kHz to MHzrange. Second, variation-resilient circuits must be designed to improve robustness without increasing V dd despite the exponential sensitivity to variations of sub-threshold circuits.To eliminate these problems, this paper proposes the use of transmission gate logic in sub-threshold combined with latch-based pipelining which improves performance, enhances variation-resilience and reduces energy consumption. Further, the transmission gate logic is extended with nMOS stacking to reduce leakage and to improve the I on /I off -ratio. Moreover, the latch-based pipeline enables time borrowing and therefore provides a means to counter the propagation delay variation in sub-threshold circuits.To prove the proposed techniques, the design of a 32 bit adder which achieves sub-pJ energy consumption combined with MHz-performance is proposed. Section II discusses the optimal gate topology for circuits operating in the weak inversion region. Section III presents the implementation of the

This paper presents a variation-resilient, complete design strategy for sub-threshold Digital Signal Processors (DSP) based on a novel combination of circuit and microarchitectural techniques of which a new differential Transmission Gate logic family is the most prominent. The strategy is successfully validated by a 16 bit, 90 nm CMOS Multiply-Accumulate (MAC) unit which operates down to a supply of 150 mV at a clock frequency of 5 MHz and 0.96 pJ energy consumption per operation. Minimum energy per operation of 0.87 pJ occurs at a supply of 190 mV and a 10 MHz clock.

This paper presents the design of variation-resilient ultra-low-voltage circuits functioning at MHz-speed. By careful design, robust digital circuits operating in the sub-threshold region are achieved. The paper discusses circuit techniques to obtain building blocks that are able to overcome the high sensitivity to variations and the decreased current ratios in sub-threshold while retaining MHz-performance. The building blocks are successfully implemented in 2 chips fabricated in 90 nm CMOS technology. Measurements show that the variation-resilient designs are fully functional at ultra-low supply voltages and obtain clock frequencies in the MHz-range and sub-pJ energy consumptions.

Operating circuits in the near-threshold region enables large energy savings. However, such circuits also pose many challenges, such as increased delay, unwanted leakage paths and high sensitivity to variations. Working in advanced nanometer CMOS technologies compromises the robustness of circuits even more due to the increased variability. Nonetheless, these technologies offer higher operating frequencies for ultra-low-voltage circuits. Transitioning to smaller technologies is attractive for digital near-threshold circuits, provided that the impact of the increased variability can be mitigated. Few prior works have considered the design of variation-resilient ultra-low-voltage circuits in CMOS technologies smaller than 65nm. The aim of this work is to design a large system that advances the state-of-the-art by not only reaching very low energy consumption, but also clock frequencies of tens of MHz, while providing high variation resilience. We present a full JPEG encoder fabricated in a 40nm CMOS technology, fully functional down to a supply voltage of 210mV. The JPEG encoder is able to operate at clock frequencies in a range from 5 to 275MHz for supplies from 210 to 550mV, and thus achieves very high ultra-low-voltage speed. At the minimum-energy point (MEP), the JPEG encoder consumes only 29.01pJ/pixel at an operating frequency of 41MHz (V DD =330mV). The variation (σ/μ) of 26 dies at this point is only 9.4% for the frequency and 6.0% for the energy consumption.

This paper demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI technology. Variability and leakage reduction strategies are employed in this new technology to achieve a state-of-the-art low energy performance. The design uses a wide range of supply voltages to reduce energy consumption per operation. The extensive back-gate biasing range allows to adapt the minimum energy point (MEP) of the circuit to the desired workload. Measurements showcase the speed/energy trade-off of both the design and the technology and lead to a MEP of 0.17pJ at 35MHz with a supply voltage of 250mV and a back-gate bias of 0.5V.