Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design

Reynders, Nele; Dehaene, Wim

doi:10.1109/tcsii.2012.2231022

Cited by 17 publications

(14 citation statements)

References 16 publications

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“…Their topology not only has a large impact on the variation-resilience of the total design, but also on the delay, leakage power and active energy consumption. It has been shown that this trade-off is most optimal when using Transmission Gate (TG) logic, extended with transistor stacking [21]. TG logic is preferred because of its higher variation-resilience and lower contribution to leakage than standard CMOS…”

Section: Logic Gatesmentioning

confidence: 99%

“…An extensive comparison between both logic families in the 90 nm CMOS technology is available in [21].…”

Section: Logic Gatesmentioning

confidence: 99%

“…The latches are controlled by non-overlapping clock signals (en a and en b) to avoid race problems. The inverter used in the latch is a stacked nMOS inverter [21]. In this case, nMOS stacking is employed to reduce the drive current I on,n , as opposed to the TG logic gates where the decreased leakage was the main reason.…”

Section: Regular Latchmentioning

confidence: 99%

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On the effect of technology scaling on variation-resilient sub-threshold circuits

Reynders

Dehaene

2015

Solid-State Electronics

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This paper studies the impact that CMOS technology scaling has on circuits operating in the ultra-lowvoltage region. Sub-threshold circuits are an attractive option for energy-constrained applications, but the influence of scaling on the energy consumption has not been studied thoroughly on on-chip ultra-low-voltage implementations. This paper aims to provide an answer to the benefits and disadvantages of scaling on such implementations. First, an equation to determine the minimum feasible supply voltage for digital circuits is derived. Out of this equation, a theoretical minimum as well as a practical minimum supply for a specific technology can be calculated. Second, a 16-bit Multiply-Accumulate Unit is selected as a test vehicle to study scaling effects. This test vehicle is designed, processed and fully measured in both a 90 nm and a 40 nm CMOS technology. An extensive comparison between the measurement results of both designs allows to clearly examine the different technology scaling trade-offs.

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Section: Logic Gatesmentioning

confidence: 99%

“…An extensive comparison between both logic families in the 90 nm CMOS technology is available in [21].…”

Section: Logic Gatesmentioning

confidence: 99%

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On the effect of technology scaling on variation-resilient sub-threshold circuits

Reynders

Dehaene

2015

Solid-State Electronics

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“…Traditionally, a balanced pull-up (PU) and pull-down (PD) network approach is preferred in logic cell design, which is important for subthreshold cell design to have a comparable PU/PD driving capability [3], [4]. Even though this can be readily achieved by either upsizing the pMOS in the PU network or stacking the nMOS in the PD network, the area overhead can lead to extra loading excessive leakage power, and also a suboptimal energy efficiency even with an identical total width as the unbalanced one [to be detailed in Fig.…”

Section: Introductionmentioning

confidence: 99%

Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques

Li¹,

Ieong²,

Law³

et al. 2015

IEEE Trans. VLSI Syst.

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Ultralow-energy biomedical applications have urged the development of a subthreshold VLSI logic family in standard CMOS. This brief proposes an unbalanced pull-up/down network, together with an inverse narrow-width technique, to improve the operating speed of the individual logic cell. Effective logical efforts save both power and die area in the process of device sizing and topology optimization. Three experimental 14-tap 8-bit finite impulse response filters optimized for ultralow-voltage operation were fabricated in 0.18-µm CMOS. Measurements show that the optimized 0.45 and 0.6 V libraries achieve minimum energy operations at 100 kHz, with a figure-of-merit of 0.365 (at 0.31 V) and 0.4632 (at 0.39 V), respectively. They correspond to 35.96% and 18.74% improvements, and the overall performances are well comparable with the state of the art. Index Terms-CMOS, device sizing, electrocardiography (ECG), finite impulse response (FIR) filter, inverse narrow width (INW), logical effort, process-voltage-temperature (PVT) variations, subthreshold standard logic library, ultralow energy, ultralow voltage.

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“…The topology of the logic gates is critical for ultra-low-voltage designs, in terms of speed, energy consumption and variation resilience. Therefore, the topology of all logic gates used throughout this JPEG encoder is based on differential transmission gate (TG) logic extended with NMOS stacking [3]. A pipeline stage is at most 3 TG logic gates deep.…”

mentioning

confidence: 99%

27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS

Reynders

Dehaene

2014

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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Operating circuits in the near-threshold region enables large energy savings. However, such circuits also pose many challenges, such as increased delay, unwanted leakage paths and high sensitivity to variations. Working in advanced nanometer CMOS technologies compromises the robustness of circuits even more due to the increased variability. Nonetheless, these technologies offer higher operating frequencies for ultra-low-voltage circuits. Transitioning to smaller technologies is attractive for digital near-threshold circuits, provided that the impact of the increased variability can be mitigated. Few prior works have considered the design of variation-resilient ultra-low-voltage circuits in CMOS technologies smaller than 65nm. The aim of this work is to design a large system that advances the state-of-the-art by not only reaching very low energy consumption, but also clock frequencies of tens of MHz, while providing high variation resilience. We present a full JPEG encoder fabricated in a 40nm CMOS technology, fully functional down to a supply voltage of 210mV. The JPEG encoder is able to operate at clock frequencies in a range from 5 to 275MHz for supplies from 210 to 550mV, and thus achieves very high ultra-low-voltage speed. At the minimum-energy point (MEP), the JPEG encoder consumes only 29.01pJ/pixel at an operating frequency of 41MHz (V DD =330mV). The variation (σ/μ) of 26 dies at this point is only 9.4% for the frequency and 6.0% for the energy consumption.

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Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design

Cited by 17 publications

References 16 publications

On the effect of technology scaling on variation-resilient sub-threshold circuits

On the effect of technology scaling on variation-resilient sub-threshold circuits

Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques

27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS

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