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Ultra-low voltage operation is key in achieving energy-efficient operation for microcontroller systems. Variation resiliency, high speed operation and short design time are the most important challenges for these systems. This paper overcomes these challenges in a new design strategy that enables standard cell design with differential transmission gate logic. The commercial toolchain is extended with in-house developed add-ons and makes use of two custom libraries with different device length to allow high speed vs. low leakage trade-offs. The design flow is used to prototype two highly efficient 32b ARM Cortex-M0 microcontroller systems in 40nm CMOS. The core of the first prototype scales down to 190mV and 0.8MHz and reaches 16.07pJ/cycle at 31.2MHz and 440mV. The second prototype benefits from the dual libraries and reduces core energy consumption by 50% at the same speed performance.Minimum energy operation is thus achieved at an even lower voltage (370mV) with the M0 core consuming only 8.80pJ/cycle at 13.7MHz, breaking the sub-10pJ/cycle barrier for a 6-35MHz range.

This paper demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI technology. Variability and leakage reduction strategies are employed in this new technology to achieve a state-of-the-art low energy performance. The design uses a wide range of supply voltages to reduce energy consumption per operation. The extensive back-gate biasing range allows to adapt the minimum energy point (MEP) of the circuit to the desired workload. Measurements showcase the speed/energy trade-off of both the design and the technology and lead to a MEP of 0.17pJ at 35MHz with a supply voltage of 250mV and a back-gate bias of 0.5V.

A 16.07pJ/cycle 31MHz Fully Differential Transmission Gate Logic ARM Cortex M0 core in 40nm CMOS