A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques

Abstract

This paper presents a pipelined 32 bit sub-threshold adder in a 90 nm CMOS technology that combines MHzperformance with sub-pJ energy consumption. To increase variation-resilience various circuit techniques are proposed, such as sub-threshold adapted transmission gate logic, optimal sizing for noise margins and time borrowing. These techniques enable operation down to a supply of 190 mV at 10 MHz and an energy consumption of 0.4 pJ per addition. A performance of 30 MHz is obtained at a supply of 260 mV and 0.6 pJ per addition. The adder achieves an improvement in Energy-Delay Product of a factor 900 compared to the state-of-the-art sub-threshold adder design. I. INTRODUCTIONUltra-low-power digital circuits have become very important due to the high demand for wireless sensor networks and medical applications. Traditional supply voltage scaling has proven to be a valuable technique to significantly reduce energy consumption. Decreasing the supply voltage below the transistor threshold voltage can provide further energy savings. However, sub-threshold operation is often limited to very low performance and suffers severely from the ever increasing variability. Until now, the focus of sub-threshold design was mainly on minimizing energy, resulting in kHz-performance [1]. Two issues must be tackled to allow the widespread use of circuits operating in the sub-threshold region. First, the performance of circuits operating at a low supply voltage in the order of a single V t must be enhanced from kHz to MHzrange. Second, variation-resilient circuits must be designed to improve robustness without increasing V dd despite the exponential sensitivity to variations of sub-threshold circuits.To eliminate these problems, this paper proposes the use of transmission gate logic in sub-threshold combined with latch-based pipelining which improves performance, enhances variation-resilience and reduces energy consumption. Further, the transmission gate logic is extended with nMOS stacking to reduce leakage and to improve the I on /I off -ratio. Moreover, the latch-based pipeline enables time borrowing and therefore provides a means to counter the propagation delay variation in sub-threshold circuits.To prove the proposed techniques, the design of a 32 bit adder which achieves sub-pJ energy consumption combined with MHz-performance is proposed. Section II discusses the optimal gate topology for circuits operating in the weak inversion region. Section III presents the implementation of the

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

“…For example as shown in Table 6 for JPEG IDCT benchmark, based on the user specified latency constraint (L cons ) and area constraint (A cons ) of 200us and 80000au, the proposed approach explores a low-cost optimal watermarked IP solution, which consumes 34062au within 101.16us. (Note: Resource characteristics with respect to 90nm technology scale, adopted from [30]- [32] are as follows: multiplier and adder have area = 2464au and 2032au, delay = 11000ns and 270ns, area of buffers and multiplexers = 126 au, respectively. Moreover, for all benchmark applications the data width of both adder and multiplier unit is 32 bits) The cost of each candidate watermarked solution is evaluated through the following function:…”

“…The delay model is based on the latency values of each functional hardware described at 90nm technology scale [32]. …”

Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency

“…the rising edge, is dominated by the weak pMOS and will only be influenced slightly by the slower stacked nMOS transistors. design, Transmission Gate (TG) logic is the most robust option for sub-threshold operation, as discussed by [2]. The variationresilience arises from the inclusion of both nMOS and pMOS transistors in each conducting path.…”

“…It is important to note that it contains only 2 inverters to minimize leakage, because the inverters leak significantly more than the TG switches. To achieve equal noise margins in this 90 nm technology, the pMOS transistors have to be sized excessively large compared to the nMOS transistors [2]. Therefore, the standard CMOS inverter is enhanced with nMOS stacking to decrease I on,n in order to relax pMOS sizing.…”

On the effect of technology scaling on variation-resilient sub-threshold circuits

“…Out of experience from previous designs (e.g. [19]), we also know that simulations to check functionality produce reliable results. Moreover, as can be seen from the variation analysis above, the intra-die simulations do show the expected increase in variability when going to a smaller technology and therefore such simulations do provide realistic results.…”