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This paper presents a new technique for detecting chip alterations using intrinsic light emission in combination with electrical test. The key idea of this method is based on the fact that any active device emits infrared light emission when it is powered on. High sensitivity photon detectors can be employed to capture the weak emission while the chip under test is powered on and electric stimuli are applied to it. In particular, two main families of electrical test modes, static and dynamic, can be applied. Positive results of the application of this methodology as well as key challenges will be discussed in the paper, including spatial resolution, imaging processing, data interpretation, etc.1.

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown (110) bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I DSat at 100 nA/um I OFF for V DD =1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from (110) silicon and an additional 8% benefit due to the compressive MOL film.

Adaptive body biasing is a promising technique for addressing increasing process variability, but it also provides new opportunities for reducing power when combined with dynamic voltage/frequency scaling. Limitations of existing ABB/DVFS proposals are explored, and a new scheme, testtime voltage selection (TTVS), is presented. By delaying the mapping between frequency and supply voltage until test, variability information can be incorporated into the VDD selection process. For a 16-core chip-multiprocessor implemented in a high-performance predictive 22 nm technology, TTVS results in 18% power savings over independent ABB/DVFS and 11% power savings over the best of several previously proposed ABB/DVFS schemes.

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