Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection

Abstract

Adaptive body biasing is a promising technique for addressing increasing process variability, but it also provides new opportunities for reducing power when combined with dynamic voltage/frequency scaling. Limitations of existing ABB/DVFS proposals are explored, and a new scheme, testtime voltage selection (TTVS), is presented. By delaying the mapping between frequency and supply voltage until test, variability information can be incorporated into the VDD selection process. For a 16-core chip-multiprocessor implemented in a high-performance predictive 22 nm technology, TTVS results in 18% power savings over independent ABB/DVFS and 11% power savings over the best of several previously proposed ABB/DVFS schemes.

Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation

“…Combining the DVFS and back-gate biasing comes naturally. Tuning of V th compliments the DVFS system and therefore many flavors of combination are explored [19], [20], [21].…”

Power management through DVFS and dynamic body biasing in FD-SOI circuits

“…[12] and [11] propose to reduce the device power consumption by reaching a constant ratio of the leakage power to the dynamic power consumption [12] or a ratio of the switching current to the leakage current [11]. However, [4] shows that the power consumption is not necessarily minimized by keeping constant the ratio of the switching current to the leakage current. [5] tries to reach a trade-off between reliability, performance and power consumption.…”

“…Unfortunately, the underlying optimization problem cannot be solved in real-time. An analysis during the circuit test-time is proposed in [4] to change V bb and V dd . The purpose is to optimize the power consumption for a given performance during the test phase.…”