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The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing. I. INTRODUCTIONTechnology scaling has traditionally enabled circuits to operate at better energy efficiency than the previous generation. While this still holds true for high-performance circuits operating near the nominal supply voltage, the increased proportion of leakage power has become a limiting factor in energy reduction for systems employing low supply voltage. As pointed in [1], recent manufacturing processes require custom-tailored standard cells to operate efficiently and reliably near the minimum energy point (MEP), where process and environment variations have great impact.In this paper, we show a method of operating logic reliably at the MEP using standard cells from the silicon provider, removing much of the overhead of custom cell design. We have implemented a 32-bit RISC CPU in 28nm CMOS, which has its energy-optimal point at near-threshold supply voltage. To minimize energy-consuming safety margins, we have utilized timing-error prevention (TEP) with adaptive clocking. TEP is a version of timing-error detection (TED) [2] [3] which has been shown to be effective in largely removing variation-incurred timing margins. The TED methodology is based on having the system operate at a voltage and frequency point in which the timing of critical paths fails intermittently. These failed timing occurrences are detected and handled (by instruction replay, etc.), whereas TEP uses adaptive margining to prevent the errors, thereby simplifying the handling process.TEP methodology and its integration to our design is elaborated in Section II. In Section III, we present system simulations which demonstrate the benefits of TEP. Finally, test chip measurements are presented in Section IV.

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Abstract:The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC-DC converter that supplies these processors is critical since energy consumption of the DC-DC/processor system is proportional to the DC-DC converter efficiency. The DC-DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC-DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm 2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter's large load power range and high efficiency make it an excellent fit for energy-constrained processors.