A Fully Integrated 2:1 Self-Oscillating Switched-Capacitor DC–DC Converter in 28 nm UTBB FD-SOI

Turnquist, Matthew J.; Hiienkari, Markus; Makipaa, Jani; Koskinen, Lauri

doi:10.3390/jlpea6030017

Cited by 2 publications

(6 citation statements)

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“…Figure 22 shows the post-layout simulation result of the voltage ripple along with a wide range load resistance RL. It changed exponentially from 90 µV to 8.43 mV, a significantly smaller ripple voltage than previous designs reported in [9,13,15]. Figure 21 shows the post-layout simulation result of the output voltage ripple for the above SSC-DVS test chip, which was obtained with a wide range of capacitor size.…”

Section: Experimental Environmentmentioning

confidence: 89%

“…The 4-bit recursive voltage converter of [14] shows 2 4 − 1 = 15 conversion ratios, while the 7-bit SAR of [9] can provide 117 conversion ratios. The designs reported in [15][16][17] show only one to three fixed conversion ratios. The proposed SSC-DVS showed an almost rail-rail output voltage range, and; thus, it could provide extremely low supply voltages to ultra-low power applications.…”

Section: Efficiencymentioning

confidence: 99%

“…The proposed SSC-DVS showed an almost rail-rail output voltage range, and; thus, it could provide extremely low supply voltages to ultra-low power applications. The design of [9] provides a limited range of supply voltages that are larger than 0.45 V, while the designs reported in [15][16][17] provide an output voltage of only 0.5 V in or higher. Furthermore, the proposed SSC-DVS showed a smaller voltage ripple of 2.656 mV.…”

Section: Efficiencymentioning

confidence: 99%

“…Moreover, the reported architecture does not offer the scalability, which is important for DVS. In other words, if we need to change the target voltage or increase the number of voltage levels, we must redesign the whole circuit.Switched-capacitor down-converters and up-converters based on the self-oscillation technique have been reported by [4,15,16]. To generate just one conversion ratio of 1:2 or 2:1, they implement an odd number of stages, usually more than three stages, with a delay circuit added between every two stages.…”

mentioning

confidence: 99%

“…Switched-capacitor down-converters and up-converters based on the self-oscillation technique have been reported by [4,15,16]. To generate just one conversion ratio of 1:2 or 2:1, they implement an odd number of stages, usually more than three stages, with a delay circuit added between every two stages.…”

mentioning

confidence: 99%

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Reference-Free Dynamic Voltage Scaler Based on Swapping Switched-Capacitors

Ragheb

Kim

2019

Energies

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This paper introduces a reference-free, scalable, and energy-efficient dynamic voltage scaler (DVS) that can be reconfigured for multiple outputs. The proposed DVS employs a novel swapping switched-capacitor (SSC) technique, which can generate target output voltages with higher resolution and smaller ripple voltages than the conventional voltage scalers based on switched-capacitors. The proposed DVS consists of a cascaded 2:1 converter based on swapping capacitors, which is essential to achieve both very small voltage ripple and fine-grain conversion ratios. One of the serious drawbacks of the conventional voltage scalers is the need for external reference voltages to maintain the target output voltage. The proposed SSC; however, eliminates the needs for any reference voltages. This significant benefit is achieved by the self-charging ability of the SSC, which can recharge all its capacitors to the configured voltage by simply swapping the two capacitors in each stage. The proposed SSC-DVS was designed with a resolution of 16 output levels and implemented using a 130 nm CMOS (Complementary Metal Oxide semiconductor) process. We conducted measured results and post-layout simulations with an input voltage of 1.5 V to produce an output voltage range of 0.085–1.4 V, which demonstrated a power efficiency of 85% for a load current of 550 µA with a voltage ripple of as low as 2.656 mV for a 2 KΩ resistor load.

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Section: Experimental Environmentmentioning

confidence: 89%