A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Abstract

The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing. I. INTRODUCTIONTechnology scaling has traditionally enabled circuits to operate at better energy efficiency than the previous generation. While this still holds true for high-performance circuits operating near the nominal supply voltage, the increased proportion of leakage power has become a limiting factor in energy reduction for systems employing low supply voltage. As pointed in [1], recent manufacturing processes require custom-tailored standard cells to operate efficiently and reliably near the minimum energy point (MEP), where process and environment variations have great impact.In this paper, we show a method of operating logic reliably at the MEP using standard cells from the silicon provider, removing much of the overhead of custom cell design. We have implemented a 32-bit RISC CPU in 28nm CMOS, which has its energy-optimal point at near-threshold supply voltage. To minimize energy-consuming safety margins, we have utilized timing-error prevention (TEP) with adaptive clocking. TEP is a version of timing-error detection (TED) [2] [3] which has been shown to be effective in largely removing variation-incurred timing margins. The TED methodology is based on having the system operate at a voltage and frequency point in which the timing of critical paths fails intermittently. These failed timing occurrences are detected and handled (by instruction replay, etc.), whereas TEP uses adaptive margining to prevent the errors, thereby simplifying the handling process.TEP methodology and its integration to our design is elaborated in Section II. In Section III, we present system simulations which demonstrate the benefits of TEP. Finally, test chip measurements are presented in Section IV.

A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads

“…There is an emerging class of energy-constrained processors that operate primarily at near-threshold (NT) voltages [1]- [5]. The processors are useful for ultra-low power sensorbased platforms which rely on low energy computation in order to reduce wireless data transmission.…”

Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS

“…Correction usually means restoring the system state and comes at the cost of a throughput reduction. Predicting errors ( [4], [5]) consists of preventing errors before they occur and corrupt the system. This prediction happens before the clock edge, taking some time out of the original clock period.…”

“…The energy overhead due to the error masking logic should be smaller than the overhead sustained by adding timing margin, resulting in an overall energy gain. While some strategies use flip-flop based pipelines ( [1], [2], [4], [6]), other use (pulsed) latches ( [2], [3], [5]). Although challenges caused by latch-based design can be overcome, flip-flop based design is generally considered more suited for timing closure.…”

SELF OSCILLATING SWITCHED- CAPACITOR DC-DC CONVERTOR USING 28nm UTBB FD-SOI

“…These processors typically operate at near-threshold (NT) voltages since operation at NT significantly reduces energy consumption but avoids the large variance and performance penalties associated with sub-threshold voltages [1]. While operating at NT, energy-constrained processors utilize multiple active and standby power modes to achieve further energy savings [2][3][4].…”

“…The relevance of energy-constrained processors [1][2][3][4][5][6] in sensor-based platforms for Internet-of-Things (IoT) applications continues to grow. These processors typically operate at near-threshold (NT) voltages since operation at NT significantly reduces energy consumption but avoids the large variance and performance penalties associated with sub-threshold voltages [1].…”