Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS

Abstract

Abstract-This paper presents a timing error masking-aware ARM Cortex M0 microcontroller system. Timing errors are detected through a timing error detection strategy, consisting of a soft edge flip-flop combined with a transition detector and an error latch. The time borrowing realized through soft edge flipflops allows data to propagate after the clock edge (timing error masking). Thus operation at the point-of-first-failure is possible, effectively eliminating any timing margin. At the same time, time borrowing events are flagged which prevents corrupting the system state and allows dynamic voltage scaling. The error-aware microcontroller was implemented in a 40nm CMOS process and realizes ultra-low voltage operation down to 0.29V at 5MHz and 12.90pJ/cycle. 37% is energy overhead due to error detection. Minumum energy operation is achieved at 7.5MHz, 0.31V and 11.11pJ/cycle. A total of 75% energy is saved when comparing to a reference design without error detection running at slow-slow corner static timing analysis speed.

A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes

“…Secondly, sub-threshold circuits are more sensitive to variations, resulting in deteriorated functionality and in highly variable gate delays. Nevertheless, research results show that these problems can be overcome in order to obtain robust digital circuits in the sub-threshold region [7][8][9][10][11]. For the performance comparison in the paper at hand, an existing standard cell library was re-characterized at 300mV supply voltage, resulting in building blocks for ultra low-voltage circuits functioning at MHz-speed.…”

Loadable Kessels Counter

“…However, this may involve among others, tuning the clock frequency. While this approach may be sufficient, two factors to be considered are the time margins of the gates [3] and part of power consumption that is affected by the operating frequency [4].…”