Loadable Kessels Counter

Abstract

We present the decomposition and implementation of a loadable self-timed counter that can perform seamless modulo loading and counting operation. The challenges in designing a loadable self-timed counter stem from the need to dynamically reconfigure operations between the counter components to arrive at the desired count modulo. The counter was decomposed into a combination of parallel and interacting computing cells as presented by Kessels. The binary equivalent for the count modulo n determined the operation of each cell in relation to its significance. Specification and verification of the counter are by formal asynchronous design methods employing Petri Nets. A 5-bits loadable counter is implemented and fabricated in 350nm CMOS process. Average power consumed at 3.3V for count 31 is in the range 89µW to 157µW. The response time of the counter after a load request is received ranges from 28.80ns to 32.71ns. Such a counter is robust and presents a practical application in timing systems like the Digital Pulse Width Modulator (DPWM) used in a DC-DC converter with fine tune control. For example, the DPWM design can sustain a variation of Vdd in the range of 3.3V to 1.8V maintaining its duty-cycle with a margin of error in the range of 1% to 7%.

A Pulse Width Modulation based Power-elastic and Robust Mixed-signal Perceptron Design

“…We believe the proposed perceptron will find practical implementations in these applications as it is highly robust to these variations. This design would nicely complement a power-elastic PWM signal generator based on a self-timed loadable modulo N counter presented in [8].…”

“…Hence, in this work we are aiming at developing a perceptron design that is resilient to power variations, i.e. power-elastic [8].…”