2015
DOI: 10.1007/978-3-319-16136-5
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Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits

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Cited by 15 publications
(3 citation statements)
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“…( 9) further justifies the necessity of terminating the xor i /xnr i signals at SCG branches and if not, V OH xor 3 further degrades through the resistive paths of SCG. Ideally, the impact of ∆V sw on the noise margin of the compressor should be minimal and both low/high noise margin levels should remain balanced at low V DD [28].…”
Section: Rd13mentioning
confidence: 99%
“…( 9) further justifies the necessity of terminating the xor i /xnr i signals at SCG branches and if not, V OH xor 3 further degrades through the resistive paths of SCG. Ideally, the impact of ∆V sw on the noise margin of the compressor should be minimal and both low/high noise margin levels should remain balanced at low V DD [28].…”
Section: Rd13mentioning
confidence: 99%
“…Operating in subthreshold is challenging for reliability reasons [11], [8]. The Noise Margin NM is used as a measure for correct functioning of a gate.…”
Section: A Design Requirementsmentioning
confidence: 99%
“…The current flowing between drain and source in the diode-connected MOS transistor in the strong inversion region (over threshold voltage) is defined by expression [21]: (1) where µ -electron mobility, ε -SiO2 permittivity, ε0electric constant (vacuum permittivity), dgate oxide thickness, Wtransistor channel width, Ltransistor channel length, Vddiodeconnected transistor voltage, Vth -threshold voltage, λchannel length modulation parameter.…”
Section: Research Of Mosfet Parameters Impact On the Output Voltagementioning
confidence: 99%